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UCC27524A-Q1

ACTIVE

Automotive 5-A/5-A dual-channel gate driver with 5-V UVLO and negative input voltage handling

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Data sheet

UCC27524A-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input VCC (min) (V) 4.5 Input VCC (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input VCC (min) (V) 4.5 Input VCC (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent Enable Function for Each Output
  • TTL and CMOS-Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Ability to Handle Negative Voltages (–5 V) at
    Inputs
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (ensures
    glitch-free operation at power-up and power-
    down)
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (7-ns and 6-ns typical)
  • 1-ns Typical Delay Matching Between 2-Channels
  • Ability to Parallel Two Outputs for High-Drive
    Current
  • Outputs Held in LOW When Inputs are Floating
  • SOIC-8 and MSOP-8 PowerPad™ Package Options
  • Operating Temperature Range of –40°C to 140°C
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent Enable Function for Each Output
  • TTL and CMOS-Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Ability to Handle Negative Voltages (–5 V) at
    Inputs
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (ensures
    glitch-free operation at power-up and power-
    down)
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (7-ns and 6-ns typical)
  • 1-ns Typical Delay Matching Between 2-Channels
  • Ability to Parallel Two Outputs for High-Drive
    Current
  • Outputs Held in LOW When Inputs are Floating
  • SOIC-8 and MSOP-8 PowerPad™ Package Options
  • Operating Temperature Range of –40°C to 140°C

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.
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Technical documentation

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Type Title Date
* Data sheet UCC27524A-Q1 Dual 5-A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. B) PDF | HTML 24 Jul 2015
Technical article Managing power-supply noise with a 30-V gate driver 07 Dec 2021
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
White paper Driving the future of HEV/EV with high-voltage solutions (Rev. B) 16 May 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC27423-4-5-Q1EVM — UCC2742xQ1 Dual 4-A High-Speed Low-Side MOSFET Drivers With Enable Evaluation Module (EVM)

The UCC2742xQ1 EVM is a high-speed dual MOSFET evaluation module that provides a test platform for a quick and easy startup of the UCC2742xQ1 driver. Powered by a single 4V to 15V external supply, and featuring a comprehensive set of test points and jumpers. All of the devices have separate input (...)
User guide: PDF
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Simulation model

UCC27524 PSpice Transient Model

SLUM243.ZIP (28 KB) - PSpice Model
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Simulation model

UCC27524 TINA-TI Transient Reference Design

SLUM257.TSC (89 KB) - TINA-TI Reference Design
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Simulation model

UCC27524 TINA-TI Transient Spice Model

SLUM256.ZIP (8 KB) - TINA-TI Spice Model
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Calculation tool

UCC2752X Schematic Review Template

SLURB22.ZIP (110 KB)
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDM-02009 — ASIL D safety concept-assessed high-speed traction, bi-directional DC/DC conversion reference design

This reference design demonstrates control of HEV/EV traction inverter and bi-directional DC-DC converter by a single TMS320F28388D real-time C2000™ MCU. The traction control uses a software-based resolver to digital converter (RDC) driving the motor to a high speed up to 20,000 RPM. The (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-020031 — Automotive 400-V battery to 12-V, 3.6-kW DC/DC converter reference design

This reference design is a 3.6-kW, automotive 400-V to 12-V unidirectional converter which converts the 200-V to 450-V DC input to 12-V, 300-A maximum output. Circuit breaker is applied for overcurrent and overvoltage protection. The converter is designed with SiC MOSFETs on the high voltage side (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
HVSSOP (DGN) 8 View options
SOIC (D) 8 View options
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