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Product details

Parameters

Type Packet switch Protocols PCIe Applications PCIe Speed (Max) (Gbps) 2.5 Supply voltage (V) 1.5, 3.3 Rating Catalog Operating temperature range (C) -40 to 85, 0 to 70 open-in-new Find other PCIe, SAS & SATA ICs

Package | Pins | Size

BGA MICROSTAR (ZHC) 196 225 mm² 15 x 15 open-in-new Find other PCIe, SAS & SATA ICs

Features

  • PCI Express Base Specification, Revision 1.1
  • PCI Express Card Electromechanical Specification, Revision 1.1
  • PCI-to-PCI Bridge Architecture Specification, Revision 1.1
  • PCI Bus Power Management Interface Specification, Revision 1.2
  • PCI Express Fanout Switch With One ×1 Upstream Port and
    Three ×1 Downstream Ports
  • Packet Transmission Starts While Reception Still in Progress (Cut-Through)
  • 256-Byte Maximum Data Payload Size
  • Peer-to-Peer Support
  • Wake Event and Beacon Support
  • Support for D1, D2, D3hot, and D3cold
  • Active State Power Management (ASPM) Using Both L0s and L1
  • Low-Power PCI Express Transmitter Mode
  • Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
  • Integrated PCI Hot Plug Support
  • Integrated REFCLK Buffers for Switch Downstream Ports
  • 3.3-V Multifunction I/O Pins for PCI Hot Plug Status and Control
    or General Purpose I/Os
  • Optional Serial EEPROM for System-Specific Configuration Register
    Initialization

PCI Express, PCI Hot Plug are trademarks of others.

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Description

The Texas Instruments XIO3130 switch is a PCI Express ×1 3-port fanout switch. The XIO3130 provides a single ×1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously. Three independently configurable ×1 downstream ports are provided that also support full 250-MB/s packet throughput in each direction simultaneously.

A cut-through architecture is implemented to reduce the latency associated with packets moving through the PCI Express fabric. As soon as the address or routing information is decoded within the header of a packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning using the EDB framing signal is supported in circumstances where packet errors are detected after the transmission of the egress packet begins.

The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario, the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is available through the classic PCI configuration space under the PCI Express Capability Structure. When enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power to the slot or socket.

Power-management features include Active State Power Management, PME mechanisms, the Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link automatically saves power when idle using the L0s and L1 states. PME messages are supported along with the PME_Turn_Off/PME_TO_Ack protocol.

When enabled, the upstream port supports Beacon transmission as well as the WAKE side band signal to wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be configured to detect Beacon from downstream devices and forward this upstream. The switch also supports the translation and forwarding of WAKE from a downstream device into Beacon on the upstream port for cabled implementations.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet XIO3130 Data Manual datasheet (Rev. F) Jan. 18, 2010
* Errata PCI Express Packet Switch Silicon Errata List (Rev. A) May 14, 2013
Application note XIO3130 Implementation Guide (Rev. A) May 03, 2012
More literature PCI Express Switch XIO3130 Quick Reference Card (Rev. B) May 16, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
299
Description

The Texas Instruments XIO3130 EVM is a functional implementation of a four-port PCIe-to-PCIe switch. The XIO3130 EVM was designed to allow validation of three separate functional modes. In normal mode the EVM is configures as a generic PCI Express switch. In Hot Plug modedownstream ports 1 and 2 are (...)

Features
  • PCI Express Base Specification, Revision 1.1
  • PCI Express Card Electromechanical Specification, Revision 1.1
  • PCI-to-PCI Bridge Architecture Specification, Revision 1.1
  • PCI Bus Power Management Interface Specification, Revision 1.2
  • PCI Express Fanout Switch With One x1 Upstream Port and Three x1 (...)

Design tools & simulation

SIMULATION MODEL Download
SLLM264.ZIP (72 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR (ZHC) 196 View options

Ordering & quality

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