*FAST is a Registered Trademark of Fairchild Semiconductor Corp.
The RCA-CD54/74AC564 and CD54/74AC574 and the CD54/74ACT564 and CD54/74ACT574 octal D-type, 3-state, positive-edge-triggered flip-flops use the RCA ADVANCED CMOS technology. The eight flip-flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE\) controls the 3-state outputs and is independent of the register operation. When the Output Enable (OE\) is HIGH, the outpus are in the high-impendance state. The CD54/74AC/ACT564 and CD54/74AC/ACT574 share the same pin configurations; the CD54/74AC/ACT564, however, has inverted outputs and the CD54/74AC/ACT574 has non-inverted outputs.
The CD74AC/ACT564 and CD74AC/ACT574 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic pakcages (M suffix). Both package types are operable over the following temperature range: Commercial (0- to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).
The CD54AC/ACT564 and CD54AC/ACT574, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Octal D-Type Flip-Flop, 3-State datasheet | 03 Dec 1998 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dec 2022 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 20 | View options |
| SOIC (DW) | 20 | View options |
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