Características para ADC34J25EVM
- Single 1.8V supply to simplify power requirements
- Flexible input clock buffer with 1/2/4 divider to simplify clocking
- On chip dither to improve SFDR
- JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
- Supports subclasses 0, 1, 2 for synchronization and compatibility
- Pin compatibility with 12/14b and dual/quad devices
Descripción de ADC34J25EVM
The ADC34J25 EVM demonstrates the performance of a low power quad 160Msps 12 bit ADC. It includes the ADC34J25 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to a 50 ohm single ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. The onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI. For a complete evaluation system, TI also offers the TSW14J50 data capture card and High Speed Data Converter Pro Software.