Información de empaque
| Encapsulado | Pines VQFN (RGE) | 24 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Transportador 250 | SMALL T&R |
Características para ADS8922B
- Resolution: 16-Bits
- High Sample Rate With No Latency Output:
- ADS8920B: 1-MSPS
- ADS8922B: 500-kSPS
- ADS8924B: 250-kSPS
- Integrated LDO Enables Single-Supply Operation
- Low Power Reference Buffer with No Droop
- Excellent AC and DC
Performance:
- SNR: 96.8-dB, THD: –125-dB
- INL: ±0.25-LSB
- DNL: ±0.2-LSB, 16-Bit No-Missing-Codes
- Wide Input
Range:
- Unipolar Differential Input Range: ±VREF
- VREF Input Range: 2.5-V to 5-V
- Single-Supply, Low-Power Operation
- Enhanced-SPI Digital Interface
- Interface SCLK: 18-MHz at 1-MSPS
- Configurable Data Parity Output
- Extended Temperature Range: –40°C to +125°C
- Small Footprint: 4-mm × 4-mm VQFN
Descripción de ADS8922B
The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.