Características para CDC7005-EVM
- Operates up to 800 MHz
- Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
- Can be used as a simple 1:5 LVPECL buffer with output dividing options
- Differential outputs programmable by serial peripheral interface (SPI)
Descripción de CDC7005-EVM
The CDC7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.
The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements by selecting the external VCXO, loop filter components, frequency for PFD, and charge pump current.
As the system requires external components like a loop filter and VCXO, this EVM provides an excellent way to evaluate and modify the performance and parameters of the clock system in conjunction with the specific customer application.