Información de empaque
| Encapsulado | Pines HTQFP (PHP) | 48 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Transportador 1,000 | LARGE T&R |
Características para DRV8340-Q1
- AEC-Q100 qualified for automotive applications
- Temperature grade 1: –40°C ≤ TA ≤ 125°C
- Three independent half-bridge gate
driver
- Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
- Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
- Smart gate drive architecture
- Adjustable slew rate control
- 1.5-mA to 1-A peak source current
- 3-mA to 2-A peak sink current
- Charge-pump of gate driver for 100% Duty Cycle
- SPI (S) and hardware (H) interface available
- 6x, 3x, 1x, and independent PWM modes
- Supports 3.3-V, and 5-V logic inputs
- Charge pump output can be used to drive the reverse supply protection MOSFET
- Linear voltage regulator, 3.3 V, 30 mA
- Integrated protection features
- VM undervoltage lockout (UVLO)
- Charge pump undervoltage (CPUV)
- Short to battery (SHT_BAT)
- Short to ground (SHT_GND)
- MOSFET overcurrent protection (OCP)
- Gate driver fault (GDF)
- Thermal warning and shutdown (OTW/OTSD)
- Fault condition indicator (nFAULT)
Descripción de DRV8340-Q1
The DRV8340-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8340-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8340-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.
The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface.
A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.