Información de empaque
| Encapsulado | Pines VQFN (RHB) | 32 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Transportador 3,000 | LARGE T&R |
Características para DRV8703-Q1
- AEC-Q100 Qualified for Automotive Applications
- Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
-
Functional Safety-Capable
- Documentation available to aid DRV8702-Q1 DRV8703-Q1 functional safety system design
- Single H-Bridge Gate Driver
- Drives Four External N-Channel MOSFETs
- Supports 100% PWM Duty Cycle
- 5.5 to 45-V Operating Supply-Voltage Range
- Three Control-Interface Options
- PH/EN, Independent H-Bridge, and PWM
- Serial Interface for Configuration (DRV8703-Q1)
- Smart Gate Drive Architecture
- Adjustable Slew-Rate Control
- Independent Control of Each H-Bridge
- Supports 1.8-V, 3.3-V, and 5-V logic inputs
- Current-Shunt Amplifier
- Integrated PWM Current Regulation
- Low-Power Sleep Mode
- Protection Features
- Supply Undervoltage Lockout (UVLO)
- Charge-Pump Undervoltage (CPUV) Lockout
- Overcurrent Protection (OCP)
- Gate-Driver Fault (GDF)
- Thermal Shutdown (TSD)
- Watchdog Timer (DRV8703-Q1)
- Fault-Condition Output (nFAULT)
Descripción de DRV8703-Q1
The DRV870x-Q1 devices are small single H-bridge gate drivers that use four external N-channel MOSFETs targeted to drive a bidirectional brushed-DC motor.
A PH/EN, independent H-Bridge, or PWM interface allows simple interfacing to controller circuits. An internal sense amplifier provides adjustable current control. Integrated Charge-Pump allows for 100% duty cycle support and can be used to drive external reverse battery switch.
Independent Half Bridge mode allows sharing of half bridges to control multiple DC motors sequentially in a cost-efficient way. The gate driver includes circuitry to regulate the winding current using fixed off-time PWM current chopping.
The DRV870x-Q1 devices include Smart Gate Drive technology to remove the need for any external gate components (resistors and Zener diodes) while protecting the external FETs. The Smart Gate Drive architecture optimizes dead time to avoid any shoot-through conditions, provides flexibility in reducing electromagnetic interference (EMI) with programmable slew-rate control and protects against any gate-short conditions. Additionally, active and passive pulldowns are included to prevent any dv/dt gate turn on.