Inicio Interfaz Serializadores-deserializadores de alta velocidad Serializadores-deserializadores FPD-Link

DS90CR286A-Q1

ACTIVO

Receptor Channel Link LVDS de +3.3 V, 28 bits, 66 MHz y flanco de subida con luz estroboscópica de d

Detalles del producto

Function Deserializer Color depth (bpp) 24 Input compatibility LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
Function Deserializer Color depth (bpp) 24 Input compatibility LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • 20 to 66 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set and Hold Times on Rx Outputs
  • Rx Power Consumption < 270 mW (Typ) at 66
    MHz Worst Case
  • Rx Power-Down Mode < 200 µW (Max)
  • ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin DGG (TSSOP)
    Package
  • Operating Temperature: −40°C to 85°C
  • Automotive Q Grade Available – AEC-Q100 Grade
    3 Qualified
  • 20 to 66 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set and Hold Times on Rx Outputs
  • Rx Power Consumption < 270 mW (Typ) at 66
    MHz Worst Case
  • Rx Power-Down Mode < 200 µW (Max)
  • ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin DGG (TSSOP)
    Package
  • Operating Temperature: −40°C to 85°C
  • Automotive Q Grade Available – AEC-Q100 Grade
    3 Qualified

The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.

The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.

The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.

The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.

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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz datasheet (Rev. H) PDF | HTML 18 ene 2016
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 ene 2016
Design guide Channel Link I Design Guide 29 mar 2007
Application note Multi-Drop Channel-Link Operation 04 oct 2004
Application note CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

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Herramienta de simulación

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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