S4MF03107SPZQQ1 ACTIVO

The TMS470MF04207/03107 devices are members of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The TMS470M devices utilize the big-endian format where the most-significant byte of a word is stored at the lowest numbered byte and the least-significant byte is stored at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The TMS470MF04207/03107 device contains the following:

• 16/32-Bit RISC CPU Core
• TMS470MF04207 Up to 448K-Byte Program Flash with SECDED ECC
• TMS470MF03107 Up to 320K-Byte Program Flash with SECDED ECC
• 64K-Byte Flash with SECDED ECC for additional program space or EEPROM Emulation
• Up to 24K-Byte Static RAM (SRAM) with SECDED ECC
• Real-Time Interrupt Timer (RTI)
• Vectored Interrupt Module
• (VIM)Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST)
• 64-bit Cyclic Redundancy Checker (CRC)
• Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module With Prescaler
• Two Multi-buffered Serial Peripheral Interfaces (MibSPI)
• Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)
• Two CAN Controller (DCAN)
• High-End Timer (HET)
• External Clock Prescale (ECP) Module
• One 16-Channel 10-Bit Multi-Buffered ADC (MibADC)
• Error Signaling Module (ESM)
• Four Dedicated General-Purpose I/O (GIO) Pins and 45 Additional Peripheral I/Os (100-Pin Package)

The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface. The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear prefetching of flash data, enables a system clock of up to 80 MHz.

The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a system reset when the watchdog counter expires.

The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs, and two MibSPIs. The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The MibSPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The MibSPI provides the standard SOMI, SIMO, and SPI clock interface as well as up to eight chip select lines.

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The TMS470M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET.

The TMS470M devices have one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be grouped by software for sequential conversion sequences. There are three separate groupings, all three of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode.

The frequency-modulated zero-pin phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides the input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2), DCAN clock (AVCLK1), and peripheral interface clock (VCLK) to all other TMS470M device modules.

The TMS470MF04207/TMS470MF03107 devices also have two external clock prescaler (ECP) modules that when enabled, output a continuous external clock (ECLK). The ECLK1 frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. The second ECLK output can be selected in place of HET15 output. It shares the same source clock as ECLK1 but can be independently programmed for a separate output frequency from ECLK1.

An error signaling module (ESM) provides a common location within the device for error reporting allowing efficient error checking and identification.