ホーム インターフェイス 高速 SerDes FPD-Link SerDes
ホーム
インターフェイス
高速 SerDes
FPD-Link SerDes

DS99R421

最終購入段階

5 ～ 43MHz、FPD-Link LVDS (3 個のデータ + 1 個のクロック) から FPD-Link II LVDS (クロック埋め込み、DC 平衡型) へのコンバータ

ご注文はこちら
データシート

DS99R421

最終購入段階
データシート ご注文はこちら

製品詳細

Function Serializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) to
Function Serializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) to

  • 5 MHz–43 MHz embedded clock & DC-Balanced data transmission (21 total LVDS data bits plus 3 low speed LVCMOS data bits)
  • User adjustable pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
  • Supports AC-coupling data transmission
  • 100Ω Integrated termination resistor at LVDS input
  • Power-down control
  • Available @SPEED BIST to DS90UR124 to validate link integrity
  • All LVCMOS inputs & control pins have internal pulldown
  • Schmitt trigger inputs on OS[2:0] to minimize metastable conditions.
  • Outputs Tri-Stated through DEN
  • On-chip filters for PLLs
  • Power supply range 3.3V ± 10%
  • Automotive temperature range −40°C to +105°C
  • Greater than 8kV ESD Tolerance
  • Meets ISO 10605 ESD and AEC-Q100 compliance
    •

  • 5 MHz–43 MHz embedded clock & DC-Balanced data transmission (21 total LVDS data bits plus 3 low speed LVCMOS data bits)
  • User adjustable pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
  • Supports AC-coupling data transmission
  • 100Ω Integrated termination resistor at LVDS input
  • Power-down control
  • Available @SPEED BIST to DS90UR124 to validate link integrity
  • All LVCMOS inputs & control pins have internal pulldown
  • Schmitt trigger inputs on OS[2:0] to minimize metastable conditions.
  • Outputs Tri-Stated through DEN
  • On-chip filters for PLLs
  • Power supply range 3.3V ± 10%
  • Automotive temperature range −40°C to +105°C
  • Greater than 8kV ESD Tolerance
  • Meets ISO 10605 ESD and AEC-Q100 compliance
    •

    The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

    The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced.

    In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

    The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

    The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced.

    In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

    filter その他の FPD-Link SerDes を検索
    ダウンロード

    技術資料

    star =TI が選定したこの製品の主要ドキュメント
    結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
    1 をすべて表示
    種類 タイトル 最新の英語版をダウンロード 日付
    * データシート 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS Converter (jp) データシート (Rev. C 翻訳版) 最新英語版 (Rev.D) PDF | HTML 2009年 9月 1日

    購入と品質

    記載されている情報：
    • RoHS
    • REACH
    • デバイスのマーキング
    • リード端子の仕上げ / ボールの原材料
    • MSL 定格 / ピーク リフロー
    • MTBF/FIT 推定値
    • 使用原材料
    • 認定試験結果
    • 継続的な信頼性モニタ試験結果
    記載されている情報：
    • ファブの拠点
    • 組み立てを実施した拠点