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AM69A

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32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX

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AM69A

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Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BXS-4-64, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES 

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BXS-4-64, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES 

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The AM69 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69 class of processors.

The AM69 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69 class of processors.
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모두 보기10
유형 제목 날짜
* Data sheet AM69x Processors, Silicon Revision 1.0 datasheet (Rev. A) PDF | HTML 2023/08/18
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. A) PDF | HTML 2023/05/20
* User guide J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C) PDF | HTML 2023/08/11
White paper Advanced AI Vision Processing Using AM69A for Smart Camera Applications PDF | HTML 2023/06/05
Application note Building an Edge AI Application for Automated Retail Scanner on AM6xA MPUs PDF | HTML 2023/05/17
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. E) PDF | HTML 2023/05/15
Application note Jacinto7 AM6x/DRA8x/TDA4x Schematic Checklist (Rev. A) PDF | HTML 2023/05/12
Application note AM6xA ISP Tuning Guide PDF | HTML 2023/03/02
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 2023/03/01
기술 기고문 How to simplify your embedded edge AI application development 2022/01/28

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평가 보드

SK-AM69 — AM69x starter kit for Sitara™ processors

The SK-AM69 Starter Kit/Evaluation Module (EVM) is based on the AM69x AI vision processor which includes an image signal processor (ISP) supporting up to 1440MP/s, 32 tera-operations-per-second (TOPS) AI accelerator, eight 64-bit Arm®-Cortex® A72 microprocessor, and H.264/H.265 video (...)

사용 설명서: PDF | HTML
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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM69A — Processor SDK Linux for AM69A

The AM69A processor software development kit (SDK) is a unified software platform includes access to benchmarks, demonstrations, drivers and more for easy setup and out-of-box development of Linux(R)-based designs. 
All releases of this SDK allow developers to seamlessly reuse and develop software (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX
하드웨어 개발
평가 보드
SK-AM69 — AM69x starter kit for Sitara™ processors
다운로드 옵션
애플리케이션 소프트웨어 및 프레임워크

MIMIK-3P-MICROSERVICES — Mimik micorservices enabled for TI's embedded processors for edge Compute

The edgeEngine Main-Child edition is specially developed for Heterogeneous Compute Platforms (HCP) such as TI-TDA4VM, TI-DRA829V, or TI-DRA821U. Along with other unique capabilities, the edgeEngine Main-Child edition provides a unique ability to dynamically execute microservices on  R5F (...)
시작: Mimik Inc.
파트너 사이트 방문
IDE, 구성, 컴파일러 또는 디버거

C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
TDA4VM — 딥 러닝, 비전 및 멀티미디어 가속기가 포함된 듀얼 Arm® Cortex®-A72 SoC 및 C7x DSP TDA4VM-Q1 — 딥 러닝을 사용하는 L2, L3 및 근거리 분석 시스템용 오토모티브 시스템 온 칩 AM62A3 — 카메라 1-2대, 저전력 시스템, 동영상 감시, 리테일 자동화용 RGB-IR ISP가 포함된 1 TOPS 비전 SoC AM62A7 — 카메라 1-2대, 저전력 시스템, 머신 비전, 로봇용 RGB-IR ISP가 포함된 2 TOPS 비전 SoC AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX AM68 — General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0 AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation
다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

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제품 세부 정보 페이지에서 지원을 확인하십시오.

제품
차량용 mmWave 레이더 센서
AWR1243 — 76GHz~81GHz 고성능 오토모티브 MMIC AWR1443 — MCU 및 하드웨어 가속기를 통합하는 싱글 칩 76~81GHz 오토모티브 레이더 센서 AWR1642 — DSP 및 MCU를 통합하는 단일 칩 76GHz~81GHz 오토모티브 레이더 센서 AWR1843 — DSP, MCU 및 레이더 가속기를 통합하는 단일 칩 76GHz~81GHz 오토모티브 레이더 센서 AWR1843AOP — 안테나 온 패키지, DSP 및 MCU가 통합된 단일 칩 76GHz~81GHz 오토모티브 레이더 센서 AWR2243 — 76GHz~81GHz 오토모티브 2세대 고성능 MMIC AWR2944 — 코너 레이더 및 전방 LRR용 76GHz~81GHz 오토모티브 2세대 고성능 SoC AWR6443 — MCU 및 레이더 가속기를 통합하는 단일 칩 60GHz~64GHz 오토모티브 레이더 센서 AWR6843 — DSP, MCU 및 레이더 가속기를 통합하는 단일 칩 60GHz~64GHz 오토모티브 레이더 센서 AWR6843AOP — 패키지, DSP 및 MCU와 안테나가 통합된 싱글 칩 60GHz~64GHz 차량용 레이더 센서
산업용 mmWave 레이더 센서
IWR1443 — MCU 및 하드웨어 가속기를 통합하는 단일 칩 76GHz~81GHz mmWave 센서 IWR1642 — DSP 및 MCU가 통합된 싱글 칩 76GHz~81GHz mmWave 센서 IWR1843 — DSP, MCU 및 레이더 가속기를 통합하는 단일 칩 76GHz~81GHz 산업용 레이더 센서 IWR6443 — MCU 및 하드웨어 가속기를 통합하는 단일 칩 60GHz~64GHz 지능형 mmWave 센서 IWR6843 — 단일 칩 60GHz~64GHz 지능형 mmWave 센서 - 처리 기능 통합 IWR6843AOP — 단일 칩 60GHz~64GHz 지능형 mmWave 센서 - 통합 안테나 온 패키지(AoP) 포함
시작 다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

EDGE-AI-STUDIO — Edge AI studio

Edge AI Studio is a collection of tools aimed to accelerate the development of edge AI application on TI embedded devices.

Model Analyzer, formerly known as TI edge AI cloud, is a free online service that allows for the evaluation of accelerated deep learning inference on remotely accessed (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
AM62A3 — 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power system, video doorbell, security camera AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, video surveillance, lawn robot AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX TDA4VM — 딥 러닝, 비전 및 멀티미디어 가속기가 포함된 듀얼 Arm® Cortex®-A72 SoC 및 C7x DSP TDA4VM-Q1 — 딥 러닝 기술을 사용하는 L2/L3, 근거리 분석 시스템을 위한 차세대 SoC 제품군
하드웨어 개발
평가 보드
J721EXCPXEVM — Jacinto™ 7 프로세서용 공통 프로세서 보드 J721EXSOMXEVM — TDA4VM 및 DRA829V 시스템 온 모듈 SK-TDA4VM — TDA4VM 에지 AI 비전 시스템용 프로세서 스타터 키트 SK-AM62A-LP — 저전력 Sitara™ 프로세서용 AM62A 스타터 키트 SK-AM68 — AM68x starter kit for Sitara™ processors SK-AM69 — AM69x starter kit for Sitara™ processors
소프트웨어
소프트웨어 개발 키트(SDK)
PROCESSOR-SDK-AM62A — Software Development Kit for AM62A Sitara processors
지원 소프트웨어
PROCESSOR-SDK-AM68A — AM68A 프로세서용 소프트웨어 개발 키트 PROCESSOR-SDK-AM69A — AM69A 프로세서용 소프트웨어 개발 키트
시작
시뮬레이션 모델

AM69A,TDA4VH-Q1,TDA4AH-Q1,TDA4VP-Q1,TDA4AP-Q1 BSDL MODEL

SPRM840.ZIP (18 KB) - BSDL Model
다운로드
시뮬레이션 모델

IBIS Model for AM69 TDA4VH TDA4AH TDA4VP TDA4AP

SPRM836.ZIP (1497 KB) - IBIS Model
다운로드
패키지 핀 다운로드
FCBGA (ALY) 1414 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링

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지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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