홈 인터페이스 고속 시리얼라이저/디시리얼라이저 FPD-Link 시리얼라이저/디시리얼라이저
홈
인터페이스
고속 시리얼라이저/디시리얼라이저
FPD-Link 시리얼라이저/디시리얼라이저

DS99R421

마지막 구매

5~43MHz FPD-Link LVDS(3 데이터 + 1 클록) - FPD-Link II LVDS(임베디드 클록 DC 균형) 컨버터

지금 주문
데이터 시트

DS99R421

마지막 구매
데이터 시트 지금 주문

제품 상세 정보

Function Serializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) to
Function Serializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) to
WQFN (NJK) 36 36 mm² 6 x 6
  • 5 MHz–43 MHz Embedded Clock & DC-Balanced Data Transmission (21 Total LVDS Data Bits Plus 3 Low Speed LVCMOS Data Bits)
  • User Adjustable Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
  • Supports AC-Coupling Data Transmission
  • 100Ω Integrated Termination Resistor at LVDS Input
  • Power-Down Control
  • Available @SPEED BIST to DS90UR124 to Validate Link Integrity
  • All LVCMOS Inputs & Control Pins Have Internal Pulldown
  • Schmitt Trigger Inputs on OS[2:0] to Minimize Metastable Conditions
  • Outputs Tri-Stated Through DEN
  • On-Chip Filters for PLLs
  • Power Supply Range 3.3V ± 10%
  • Automotive Temperature Range −40°C to +105°C
  • Greater Than 8kV ESD Tolerance
  • Meets ISO 10605 ESD and AEC-Q100 Compliance

All trademarks are the property of their respective owners.

  • 5 MHz–43 MHz Embedded Clock & DC-Balanced Data Transmission (21 Total LVDS Data Bits Plus 3 Low Speed LVCMOS Data Bits)
  • User Adjustable Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
  • Supports AC-Coupling Data Transmission
  • 100Ω Integrated Termination Resistor at LVDS Input
  • Power-Down Control
  • Available @SPEED BIST to DS90UR124 to Validate Link Integrity
  • All LVCMOS Inputs & Control Pins Have Internal Pulldown
  • Schmitt Trigger Inputs on OS[2:0] to Minimize Metastable Conditions
  • Outputs Tri-Stated Through DEN
  • On-Chip Filters for PLLs
  • Power Supply Range 3.3V ± 10%
  • Automotive Temperature Range −40°C to +105°C
  • Greater Than 8kV ESD Tolerance
  • Meets ISO 10605 ESD and AEC-Q100 Compliance

All trademarks are the property of their respective owners.

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

filter 기타 FPD-Link 시리얼라이저/디시리얼라이저 찾기
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기술 자료

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유형 직함 날짜
* Data sheet 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS Converter datasheet (Rev. D) 2013/04/16

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치