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The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.
The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module.
Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface.
The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current.
The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) NFBGA and WQFN packages.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer datasheet (Rev. L) | 02 May 2013 | |
| Application note | Mobile Pixel Link Level-0 | 20 Mar 2012 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| WQFN (RSB) | 40 | View options |
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