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SN54AC74-SP

ACTIVE

Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset

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Data sheet

SN54AC74-SP

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family AC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 2 Technology family AC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Space
CFP (W) 14 58.023 mm² 9.21 x 6.3
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 10 ns at 5 V
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 10 ns at 5 V

The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
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Technical documentation

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Type Title Date
* Data sheet SN54AC74, SN74AC74 datasheet (Rev. F) 23 Oct 2003
* SMD SN54AC74-SP SMD 5962-88520 08 Jul 2016
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Selection guide TI Space Products (Rev. I) 03 Mar 2022
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Selection guide Logic Guide (Rev. AB) 12 Jun 2017
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Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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