Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down
    Mode, and Back Drive Protection
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down
    Mode, and Back Drive Protection
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

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* Data sheet SNx4LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. I) PDF | HTML 17 Feb 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV126A Behavioral SPICE Model

SCEM656.ZIP (7 KB) - PSpice Model
Simulation model

SN74LV126A IBIS Model

SCEM127.ZIP (18 KB) - IBIS Model
Package Pins Download
SOIC (D) 14 View options
SOP (NS) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

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