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音訊與雷達 DSP SoC

66AK2G12

現行

高效能多核心 DSP+Arm - 1x Arm A15 核心、1x C66x DSP 核心

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產品規格表
使用指南

66AK2G12

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A15 Frequency (MHz) 600, 1000 Coprocessors C66x DSP Display type 1 LCD PCIe 1 PCIe Gen 2 Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Secure boot, Secure storage Rating Catalog Operating temperature range (°C) -40 to 125
CPU 1 Arm Cortex-A15 Frequency (MHz) 600, 1000 Coprocessors C66x DSP Display type 1 LCD PCIe 1 PCIe Gen 2 Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Secure boot, Secure storage Rating Catalog Operating temperature range (°C) -40 to 125
FCCSP (ABY) 625 441 mm² (21 mm × 21 mm)
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 66AK2G1x Multicore DSP+Arm KeyStone II System-on-Chip (SoC) datasheet (Rev. F) PDF | HTML 2019/12/10
* 使用指南 66AK2Gx Multicore DSP + ARM Keystone II System-on-Chip (SOC) TRM (Rev. I) 2019/2/25
* 使用指南 K2G General Purpose Evaluation Module (EVMK2G) TRM (Rev. A) 2017/9/20
* 勘誤表 66AK2G1x Errata (Rev. B) 2018/6/20
應用說明 Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025/9/3
應用說明 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/2/24
應用說明 PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022/10/11
應用說明 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/7/7
應用說明 Keystone Error Detection and Correction EDC ECC (Rev. A) 2021/6/25
應用說明 How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/5/19
應用說明 Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019/6/11
應用說明 KeyStone II DDR3 interface bring-up PDF | HTML 2019/3/7
白皮書 Designing professional audio mixers for every scenario 2018/6/28
設計指南 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems (Rev. B) 2018/6/12
應用說明 66AK2G1x: EVMK2GX General-Purpose EVM Power Distribution Network Analysis 2018/3/14
使用指南 PRU Assembly Instruction User Guide 2018/2/16
應用說明 66AK2G12 Power Consumption Summary 2018/2/9
應用說明 66AK2G12 Power Estimation Tool 2018/1/19
使用指南 TPS65911A User’s Guide for 66AK2G12 Processor (Rev. A) 2017/12/18
使用指南 66AK2Gx BGA Escape Routing Stackup (Rev. A) 2017/11/14
使用指南 66AK2Gx Hardware Design Guide (Rev. A) 2017/11/14
應用說明 66AK2Gx Schematic Checklist (Rev. A) 2017/11/14
白皮書 Designing Embedded Systems for High Reliability With 66AK2Gx (Rev. A) 2017/8/28
白皮書 Getting personal with the 66AK2Gx SoC (Rev. A) 2017/8/2
更多文件說明 K2G General-Purpose (GP) EVM Quick Start Guide (Rev. A) 2017/7/27
白皮書 Voice as the user interface – a new era in speech processing white Paper 2017/5/9
應用說明 Processor SDK RTOS Audio Benchmark Starter Kit 2017/4/12
使用指南 K2G Industrial Communications Engine (K2G ICE) 2017/2/28
更多文件說明 K2G Industrial Communications Engine (ICE) Quick Start Guide 2017/2/2
使用指南 TPS659118 User’s Guide for 66AK2G02 Processor 2016/5/2
應用說明 SERDES Link Commissioning on KeyStone I and II Devices 2016/4/13
更多文件說明 K2G Audio Daughter Card Quick Start Guide 2016/3/14
白皮書 Multicore SoCs stay a step ahead of SoC FPGAs 2016/2/23
應用說明 TI DSP Benchmarking PDF | HTML 2016/1/13
應用說明 Keystone II DDR3 Debug Guide 2015/10/16
應用說明 Keystone II DDR3 Initialization 2015/1/26
應用說明 Hardware Design Guide for KeyStone II Devices 2014/3/24
使用指南 C66x CorePac User's Guide (Rev. C) 2013/6/28
應用說明 Introduction to TMS320C6000 DSP Optimization 2011/10/6
白皮書 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011/5/19
使用指南 C66x CPU and Instruction Set Reference Guide 2010/11/9
使用指南 C66x DSP Cache User's Guide 2010/11/9

設計與開發

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開發套件

EVMK2GX — 66AK2Gx 1GHz 評估模組

EVMK2GX（亦稱為「K2G」）1GHz 評估模組 (EVM) 可讓開發人員立即開始評估 66AK2Gx 處理器系列，並加快音訊、工業馬達控制、智慧電網保護和其他高可靠性，即時運算密集應用的開發速度。66AK2Gx 與現有的 KeyStone 式 SoC 裝置類似，可讓 DSP 與 Arm® 核心控制系統中的所有記憶體和週邊設備。此架構有助於實現最大軟體彈性以及以 DSP 或 Arm 為中心的系統設計。

此 EVM 受 Linux 和 TI-RTOS 作業系統的處理器 SDK 支援，並具備 USB、PCIe 與 Gigabit 乙太網路等關鍵週邊設備。它包括電路板管理控制器、SD (...)

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子卡

AUDK2G — 66AK2Gx (K2G) 音訊子卡

K2G 音訊子卡是為了與 K2G 通用 EVM (EVMK2G) 或 EVMK2GX 配合使用而設計的，音訊子卡的操作需要 EVMK2G 或 EVMK2GX。  此子卡可讓使用者開發多聲道音訊應用，例如以 66AKG2G02 DSP + Arm® 處理器 SoC 為基礎的 A/V 接收器、音響、汽車擴大器系統和混音控制台。

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2G — Linux Processor SDK for K2Gx

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2G — Linux-RT Processor SDK for K2G

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-K2G — TI-RTOS Processor SDK for K2Gx (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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驅動程式或資料庫

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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驅動程式或資料庫

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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驅動程式或資料庫

PRU-ICSS-INDUSTRIAL-SW — 適用於 Sitara™ 處理器的 PRU-ICSS 工業軟體

PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。  PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。  (...)

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驅動程式或資料庫

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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軟體轉碼器

AURO-3P-3DENGINE — Auro Technologies Auro 轉碼器和 Auro-Matic 軟體

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
從：Auro Technologies N.V.
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模擬型號

66AK2G12 BSDL Model

SPRM715.ZIP (24 KB) - BSDL 模型
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模擬型號

66AK2G12 IBIS Model

SPRM705.ZIP (1918 KB) - IBIS 模型
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模擬型號

66AK2G12 Thermal Model

SPRM716.ZIP (3 KB) - 熱模型
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI 模型
lock = 需要匯出核准 (1 分鐘)
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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參考設計

TIDEP-0088 — 適用於基於語音的應用的音訊預處理系統參考設計

此參考設計使用多個麥克風、波束成形演算法和其他程序，在雜音和其他干擾中擷提取清晰的語音和音訊。  在易受噪音影響的環境中，使用語音啟動數位助理的應用程式迅速增加，對於能夠在嘈雜環境中擷取清晰語音的系統，其需求也應運而生。  此參考設計採用麥克風陣列與先進訊號處理技術，能從嘈雜環境中擷取清晰音訊。
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參考設計

TIDEP0067 — 66AK2Gx DSP + ARM 處理器電源解決方案參考設計

此參考設計是以 66AK2Gx 多核心系統單晶片 (SoC) 處理器和配套 TPS65911 電源管理積體電路 (PMIC) 為基礎，其在單一裝置中包含 66AK2Gx 處理器的電源供應器和電源排序。此電源解決方案設計也包括支援 12V 輸入的第一級降壓轉換器，以及適用於 DDR3L 記憶體的 DDR 終端穩壓器。參考設計經過測試，並包含硬體參考 (EVM)、軟體（處理器 SDK）和測試資料。
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參考設計

TIDEP0068 — 適用於 K2G 通用 EVM (GP EVM) 的 PCI-Express PCB 設計注意事項參考設計

PCI-Express 提供低接腳數、高可靠度與高速傳輸功能，資料傳輸速率每通道每方向可達 5.0 Gbps，且 TI 66AK2Gx DSP + ARM 處理器系統單晶片 (SoC) 內含 PCIe 模組。  本 PCIe 印刷電路板設計考量參考設計，透過提供 66AK2Gx 處理器 SoC 中 PCIe 部分的最佳化 PCB 實踐，協助開發人員優化印刷電路板 (PCB) 設計。  此舉進而讓開發人員能在第一次 PCB 實作中即達成所需的 PCIe 訊號效能，快速專注於以 K2G 處理器為基礎的應用開發與測試。  66AK2Gx 通用評估 EVM (EVMK2G) (...)

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參考設計

TIDEP0069 — 66AK2Gx DSP + ARM 處理器音訊處理參考設計

此參考設計為一參考平台，以 66AK2Gx DSP + ARM 處理器系統單晶片 (SoC) 和配套 AIC3106 音訊編解碼器為基礎，可快速實現音訊處理演算法設計與展示。此音訊解決方案設計包括使用處理器 SDK TI RTOS 軟體的即時應用軟體，可展示 DSP 上的音訊處理區塊以新增音訊效果。 
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參考設計

TIDEP0070 — 用於在 66AK2Gx 系統中提高記憶體可靠性的 DDR ECC 參考設計

此參考設計以 66AK2Gx 多核心 DSP + ARM 處理器系統單晶片 (SoC) 為基礎，說明高可靠性應用中支援錯誤修正程式碼 (ECC) 的雙資料速率 (DDR) 記憶體介面之系統考量。  該設計能讓開發人員討論系統介面、電路板硬體、軟體、輸送量性能及診斷程序，快速實作高可靠性的解決方案。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (ABY) 625 Ultra Librarian
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