ADC34J23EVM 的特色
- Single 1.8V supply to simplify power requirements
- Flexible input clock buffer with 1/2/4 divider to simplify clocking
- On chip dither to improve SFDR
- JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
- Supports subclasses 0,1,2 for synchronization and compatibility
ADC34J23EVM 的說明
The ADC34J23 evaluation module demonstrates the performance of a low power quad 80Msps 12 bit ADC. It includes the ADC34J23 device, LMK04828 to provide JESD204B clocking and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm single ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI.