封裝資訊
| 封裝 | 引腳 VQFN (RGZ) | 48 |
| 作業溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送包裝 2,500 | LARGE T&R |
ADS58B19 的特色
- ADS58B18: 11-Bit, 200MSPS
- ADS58B19: 9-Bit, 250MSPS
- Integrated High-Impedance Analog Input Buffer
- Ultralow Power:
- Analog Power: 258mW at 200MSPS
- I/O Power: 69mW (DDR LVDS, low LVDS swing)
- High Dynamic Performance:
- ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
- ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
- Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
- –77.7dBFS SNR in 20MHz Bandwidth
- Dynamic Power Scaling with Sample Rate
- Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100Ω Termination
- 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Programmable Gain for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- Package: QFN-48 (7mm × 7mm)
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
ADS58B19 的說明
The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).
Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).