289-pin (ZBV) package image

AFE58JD32ZBV 現行

具有 42-mW/通道功率、數位解調器以及 JESD204B 和 LVDS 介面的 32 通道超音波 AFE

定價

數量 價格
+

品質資訊

等級 Catalog
RoHS
REACH
引腳鍍層 / 焊球材質 SNAGCU
MSL 等級 / 迴焊峰值 Level-3-260C-168 HR
品質、可靠性
及包裝資訊

內含資訊:

  • RoHS
  • REACH
  • 產品標記
  • 引腳鍍層 / 焊球材質
  • MSL 等級 / 迴焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中可靠性監測
檢視或下載
其他製造資訊

內含資訊:

  • 晶圓廠位置
  • 組裝地點
檢視

出口分類

*僅供參考

  • 美國 ECCN:EAR99

封裝資訊

封裝 | 引腳 NFBGA (ZBV) | 289
作業溫度範圍 (°C) -40 to 85
包裝數量 | 運送包裝 126 | JEDEC TRAY (5+1)

AFE58JD32 的特色

  • 32-Channel, AFE for Ultrasound Applications:
    • Input Attenuator, LNA, LPF, ADC,
      Digital I/Q Demodulator and CW Mixer
    • Digital Time Gain Compensation (DTGC)
    • Total Gain Range: 12 dB to 51 dB
    • Linear Input Range: 800 mVPP
  • Input Attenuator With DTGC:
    • 8-dB to 0-dB Attenuation With 0.125-dB Step
    • Supports Matched Impedance for:
      • 50-Ω to 800-Ω Source Impedance
  • Low-Noise Amplifier (LNA) With DTGC:
    • 20-dB to 51-dB Gain With 0.125-dB Step
    • Low Input Current Noise: 1.2 pA/√Hz
  • 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
    • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
  • 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
    • Each ADC Converts Two Sets of Inputs at Half Rate
    • 12-Bit ADC: 72-dBFS SNR
    • 10-Bit ADC: 61-dBFS SNR
  • Optimized for Noise and Power:
    • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
    • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
    • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
    • 60 mW/Ch in CW Mode
  • Excellent Device-to-Device Gain Matching:
    • ±0.5 dB (Typical)
  • Low Harmonic Distortion: –55 dBc
  • Fast and Consistent Overload Recovery
  • Continuous Wave (CW) Path With:
    • Low Close-In Phase Noise of –151 dBc/Hz
      at 1-kHz Frequency Offset Off 2.5-MHz Carrier
    • Phase Resolution: λ / 16
    • Supports 16X CW Clock
    • 12-dB Suppression on Third and Fifth Harmonics
  • Digital I/Q Demodulator After ADC:
    • Decimation Filter M = 1 to 63
    • Data Throughput Reduction After Decimation
    • On-Chip RAM with 32 Preset Profiles
  • LVDS Interface With a Speed Up to 1 Gbps
  • 5-Gbps JESD Interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
  • Small Package: 15-mm × 15-mm NFBGA-289

AFE58JD32 的說明

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.

The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).

The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to be selected for optimizing system performance. Therefore, this device is a suitable ultrasound AFE solution for systems with strict battery-life requirements.

定價

數量 價格
+

包裝類型選項

您可依零件數量選擇不同包裝類型選項,包含完整捲盤、客製化捲盤、剪切捲帶、承載管或盤。

客製化捲盤是從一個捲盤上剪切下來的連續剪切捲帶,以維持批次和日期代碼可追溯性,依要求剪切至確切數量。依照業界標準,銅墊片會在剪切捲帶兩側連接 18 英吋前後導帶,以直接送至自動組裝機器。針對客製化捲盤訂單,TI 將酌收捲帶封裝費用。

剪切捲帶是從捲盤剪切下來的一段捲帶。TI 可能使用多條剪切捲帶或承載盒,以滿足訂單要求數量。

TI 常以盒裝或管裝、盤裝方式運送承載管裝置,視現有庫存而定。所有捲帶、管或樣本盒之封裝,皆符合公司內部靜電放電與防潮保護包裝要求。

進一步了解

可提供批次和日期代碼選擇

在購物車中加入數量,並開始結帳流程以檢視可用選項,從現有庫存中選擇批次或日期代碼。

進一步了解