DS90LT012AQ-Q1

現行

車用 LVDS 差動線路接收器

產品詳細資料

Function Receiver Protocols CML, LVDS, LVPECL Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CML, LVDS, LVPECL Output signal CMOS Rating Automotive Operating temperature range (°C) -40 to 125
Function Receiver Protocols CML, LVDS, LVPECL Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CML, LVDS, LVPECL Output signal CMOS Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8
  • AECQ-100 Grade 1
  • -40 to +125°C Temperature Range Operation
  • Compatible with ANSI TIA/EIA-644-A Standard
  • >400 Mbps (200 MHz) Switching Rates
  • 100 ps Differential Skew (Typical)
  • 3.5 ns Maximum Propagation Delay
  • Integrated Line Termination Resistor (100Ω Typical)
  • Single 3.3V power supply design
  • Power Down High Impedance on LVDS Inputs
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Pinout Simplifies PCB Layout
  • Low Power Dissipation (10mW Typical@ 3.3V Static)
  • SOT-23 5-Lead Package

All trademarks are the property of their respective owners.

  • AECQ-100 Grade 1
  • -40 to +125°C Temperature Range Operation
  • Compatible with ANSI TIA/EIA-644-A Standard
  • >400 Mbps (200 MHz) Switching Rates
  • 100 ps Differential Skew (Typical)
  • 3.5 ns Maximum Propagation Delay
  • Integrated Line Termination Resistor (100Ω Typical)
  • Single 3.3V power supply design
  • Power Down High Impedance on LVDS Inputs
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Pinout Simplifies PCB Layout
  • Low Power Dissipation (10mW Typical@ 3.3V Static)
  • SOT-23 5-Lead Package

All trademarks are the property of their respective owners.

The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology

The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications.

The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.

The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology

The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications.

The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.

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類型 標題 日期
* Data sheet DS90LT012AQ Automotive LVDS Differential Line Receiver datasheet (Rev. E) 2013年 4月 17日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application note AN-1821 CPRI Repeater System (Rev. A) 2013年 4月 26日
Application note An Overview of LVDS Technology 1998年 10月 5日

設計與開發

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開發板

DS90LV047-48AEVM — DS90LV047-48AEVM 評估模組

The DS90LV047-48AEVM is an evaluation module (EVM) designed for performance and functional evaluation of Texas Instruments' DS90LV047A 3-V LVDS quad CMOS differential line driver and DS90LV048A 3-V LVDS CMOS differential line receiver. With this kit, users can quickly evaluate the output (...)
使用指南: PDF
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模擬型號

DS90LT012A IBIS Model

SNLM044.ZIP (11 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

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模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計

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Design guide: PDF
電路圖: PDF
參考設計

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This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Design guide: PDF
電路圖: PDF
參考設計

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This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能

此參考設計可解決與新興 5G 適配應用相關,例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化,這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器,透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能,在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果,以進一步降低偏斜。此設計也具備搭載 (...)
Design guide: PDF
電路圖: PDF
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SOT-23 (DBV) 5 Ultra Librarian

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