DS90UR908Q-Q1

現行

5 - 65 MHz 24 位元彩色 FPD-Link II 至 FPD-Link 轉換器

產品詳細資料

Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility FPD-Link LVDS Color depth (bpp) 24 Features I2C Config Signal conditioning Programmable Equalizer EMI reduction BIST Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility FPD-Link LVDS Color depth (bpp) 24 Features I2C Config Signal conditioning Programmable Equalizer EMI reduction BIST Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • 5 – 65 MHz Support (140 Mbps to 1.82 Gbps Serial Link)
  • 5-Channel (4 data + 1 clock) FPD-Link Driver Outputs
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Input Termination
  • @ Speed link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB888 + VS, HS, DE Support
  • Power Down Mode Minimizes Power Dissipation
  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receive Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • Low EMI FPD-Link Output
  • SSCG Option for Lower EMI
  • 1.8V or 3.3V Compatible I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8kV HBM ESD Tolerance
  • Backward Compatible Mode For Operation with Older Generation Devices

All trademarks are the property of their respective owners.

  • 5 – 65 MHz Support (140 Mbps to 1.82 Gbps Serial Link)
  • 5-Channel (4 data + 1 clock) FPD-Link Driver Outputs
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Input Termination
  • @ Speed link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB888 + VS, HS, DE Support
  • Power Down Mode Minimizes Power Dissipation
  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receive Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • Low EMI FPD-Link Output
  • SSCG Option for Lower EMI
  • 1.8V or 3.3V Compatible I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8kV HBM ESD Tolerance
  • Backward Compatible Mode For Operation with Older Generation Devices

All trademarks are the property of their respective owners.

The DS90UR908Q converts FPD-Link II to FPD Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to four LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS90UR908Q converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output voltage level select feature, and additional output spread spectrum generation.

With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer.

The DS90UR908Q is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 grade 2 temperature range of -40˚C to +105˚C.

The DS90UR908Q converts FPD-Link II to FPD Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to four LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS90UR908Q converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output voltage level select feature, and additional output spread spectrum generation.

With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer.

The DS90UR908Q is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 grade 2 temperature range of -40˚C to +105˚C.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DS90UR908Q 5-65 MHz 24-bit Color FPD-Link II to FPD-Link Conv datasheet (Rev. H) 2013/4/16
應用說明 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 2013/4/29
應用說明 Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) 2013/4/26
應用說明 AN-1807 FPD-Link II Display SerDes Overview (Rev. B) 2013/4/26
使用指南 DS90UR908Q-EVK FPD-Link II to FPD-Link Converter Evaluation Kit 2012/1/26

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模擬型號

DS90UR908Q IBIS Model

SNLM117.ZIP (172 KB) - IBIS 模型
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (RHS) 48 Ultra Librarian

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