SM320C6678-HIREL

現行

高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP

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產品規格表

document-pdfAcrobat SM320C6678-HIREL Multicore Fixed and Floating-Point Digital Signal Processor datasheet (Rev. A) (英文)

SM320C6678-HIREL

現行

產品規格表

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產品詳細資料

CPU

32-/64-bit

Frequency (MHz)

1000

PCIe

2 PCIe Gen2

Hardware accelerators

Operating system

DSP/BIOS

Security

Cryptographic acceleration

Rating

High Temp

Operating temperature range (°C)

-55 to 115

CPU

32-/64-bit

Frequency (MHz)

1000

PCIe

2 PCIe Gen2

Hardware accelerators

Operating system

DSP/BIOS

Security

Cryptographic acceleration

Rating

High Temp

Operating temperature range (°C)

-55 to 115

FCBGA (CYP)

841

576 mm² (24 mm × 24 mm)

Eight SM320C66x DSP Core Subsystems at 1.00 GHz
- 32KB L1P, 32KB L1D, 512KB L2 Per Core
- 4MB Shared L2
Multicore Navigator and TeraNet Switch Fabric - 2 Tb
Network Coprocessors- Packet Accelerator, Security Accelerator
Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
HyperLink - Up to 50Gbaud Operation at -40C to 105C and 25 GBaud at -55C to 115C, Full Duplex
Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
UART Interface
I2C Interface
16 GPIO Pins
SPI Interface
Sixteen 64-Bit Timers
Three On-Chip PLLs

Eight SM320C66x DSP Core Subsystems at 1.00 GHz
- 32KB L1P, 32KB L1D, 512KB L2 Per Core
- 4MB Shared L2
Multicore Navigator and TeraNet Switch Fabric - 2 Tb
Network Coprocessors- Packet Accelerator, Security Accelerator
Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
HyperLink - Up to 50Gbaud Operation at -40C to 105C and 25 GBaud at -55C to 115C, Full Duplex
Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
UART Interface
I2C Interface
16 GPIO Pins
SPI Interface
Sixteen 64-Bit Timers
Three On-Chip PLLs

The SM320C6678 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with eight C66x CorePac DSPs, each core runs at 1.0 GHz enabling up to 8 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6678 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

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重要文件	類型	標題	格式選項	日期
*	資料表	SM320C6678-HIREL Multicore Fixed and Floating-Point Digital Signal Processor datasheet (Rev. A)		2014/4/3
*	勘誤表	TMS320C6678 Multcore Fixed & Floating-Point DSP Silicon Errata (Revs 1.0, 2.0) (Rev. H)		2015/6/29
	應用說明	DDR3 Design Requirements for KeyStone Devices (Rev. D)	PDF \| HTML	2022/7/7
	使用指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/6/1
	應用說明	Hardware Design Guide for KeyStone Devices (Rev. D)	PDF \| HTML	2019/3/21
	應用說明	Thermal Design Guide for DSP and Arm Application Processors (Rev. B)		2017/8/14
	使用指南	Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)		2017/7/26
	應用說明	KeyStone I DDR3 Initialization (Rev. E)		2016/10/28
	使用指南	Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)	PDF \| HTML	2015/5/6
	使用指南	Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)	PDF \| HTML	2015/4/9
	使用指南	DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)		2015/1/20
	使用指南	Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)		2014/9/4
	使用指南	Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)		2014/9/3
	使用指南	System Analyzer User's Guide (Rev. F)		2013/11/18
	使用指南	PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)		2013/9/30
	使用指南	DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)		2013/7/15
	白皮書	Another Look at the Future of Medical Processing		2013/7/12
	白皮書	Medical Software Development on Keystone Devices		2013/7/12
	白皮書	Accelerating high-performance computing development with Desktop Linux SDK		2013/7/8
	使用指南	Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)		2013/7/3
	使用指南	Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)		2013/6/28
	使用指南	C66x CorePac User's Guide (Rev. C)		2013/6/28
	使用指南	HyperLink for KeyStone Devices User's Guide (Rev. C)		2013/5/28
	使用指南	Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)		2013/2/5
	Product overview	Multicore DSPs for High-Performance Video Coding		2013/1/22
	Product overview	OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A)		2012/11/5
	應用說明	SerDes Implementation Guidelines for KeyStone I Devices		2012/10/31
	Product overview	TMS320C66x high-performance multicore DSPs for video surveillance		2012/9/6
	應用說明	Multicore Programming Guide (Rev. B)		2012/8/29
	使用指南	TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)		2012/8/21
	使用指南	TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)		2012/8/21
	使用指南	Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)		2012/7/11
	白皮書	Leveraging multicore processors for machine vision applications		2012/5/9
	使用指南	Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)		2012/4/24
	Product overview	TMS320C6678 Multicore DSP for Multimedia Infrastructure (Rev. A)		2012/4/11
	使用指南	Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)		2012/3/30
	使用指南	Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)		2012/3/27
	使用指南	64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)		2012/3/22
	白皮書	Maximizing Multicore Efficiency with Navigator Runtime		2012/2/23
	白皮書	Comparing TI's TMS320C6671 DSP with ADI’s ADSP-TS201S TigerSHARC Processor (Rev. A)		2012/1/6
	應用說明	PCIe Use Cases for KeyStone Devices		2011/12/13
	使用指南	Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)		2011/10/15
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	Debug and Trace for KeyStone I Devices User's Guide (Rev. A)		2011/9/22
	使用指南	Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide		2011/9/2
	白皮書	KeyStone Multicore SoC Tool Suite: one platform for all needs		2011/6/17
	使用指南	External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)		2011/5/24
	白皮書	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		2011/5/19
	Product overview	TMS320C6671/72/74/78 High-Performance Multicore Fixed- and Floating-Point DSPs (Rev. B)		2011/4/25
	應用說明	TMS320C66x DSP Generation of Devices (Rev. A)		2011/4/25
	白皮書	Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP		2011/3/16
	白皮書	Software-Based Ultrasound Beamforming on Multicore DSPs		2011/3/6
	白皮書	KeyStone Memory Architecture White Paper (Rev. A)		2010/12/21
	應用說明	Optimizing Loops on the C66x DSP		2010/11/9
	使用指南	General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide		2010/11/9
	使用指南	C66x CPU and Instruction Set Reference Guide		2010/11/9
	應用說明	Clocking Design Guide for KeyStone Devices		2010/11/9
	使用指南	Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG		2010/11/9
	使用指南	C66x DSP Cache User's Guide		2010/11/9
	使用指南	Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide		2010/11/9
	使用指南	Network Coprocessor for KeyStone Devices User's Guide		2010/11/2

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所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

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AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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C64X-DSPLIB — Download TMS320C64x DSP Library

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C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices

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FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

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VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

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