首頁 介面 LVDS、M-LVDS 和 PECL IC
首頁
介面
LVDS、M-LVDS 和 PECL IC

SN65LV1023A

現行

10:1 LVDS 串聯器/解串器發射器 100 - 660Mbps

立即訂購
產品規格表
勘誤表

SN65LV1023A

現行
產品規格表 立即訂購

產品詳細資料

Function Serializer Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (Mbps) 660 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Serializer Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (Mbps) 660 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DB) 28 79.56 mm² 10.2 x 7.8 VQFN (RHB) 32 25 mm² 5 x 5
  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM
  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.
filter 尋找其它 LVDS、M-LVDS 和 PECL IC
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 5
類型 標題 日期
* Data sheet 10-MHz to 66-MHz, 10:1-LVDS Serializer/Deserializer datasheet (Rev. E) 2009年 12月 7日
* Errata SN65LV1023A Sync Pattern Generation Logic Error 2003年 6月 26日
Application note Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 2020年 10月 29日
Application brief Migrating from DS92LV1021A/1212A 10-bit SerDes to SN65LV1023A/1224B 2018年 11月 15日
User guide 10:1 Serializer/Deserializer Evaluation Board 2013年 11月 20日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN65LV1023A IBIS Model

SLLM358.ZIP (31 KB) - IBIS Model
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
View Options
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DB) 28 Ultra Librarian
VQFN (RHB) 32 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片