全雙工 M-LVDS 收發器

SN65MLVD202 不建議用於新設計
儘管為了支援以前的設計而繼續生產此項產品,但我們並不建議用在新設計上。考量下列其中一項替代產品:
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功能相似於所比較的產品
SN65MLVD202A 現行 全雙工 M-LVDS 收發器 This is a newer generation of this product

產品詳細資料

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 100 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 100 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6
  • Low-Voltage Differential 30- up to 100 Mbps
  • Power Dissipation at 100 Mbps
    • Driver: 50 mW Typical
    • Receiver: 30 mW Typical
  • Meets or Exceeds Current Revision of M-LVDS Standard TIA/EIA–899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1-V to 3.4-V Common-Mode Voltage Range Allows Data Transfer With up to 2 V of Ground Noise
  • Type-1 Receivers Incorporate 25 mV of Hysteresis
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Operates From a Single 3.3-V Supply
  • Propagation Delay Times Typically 2.3 ns for Drivers and 5 ns for Receivers
  • Power-Up/Down Glitch-Free Driver
  • Driver Handles Operation Into a Continuous Short Circuit Without Damage
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
  • 200-Mbps Devices Available (SN65MLVD201, 203, 206, and 207)

The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second) units.

  • Low-Voltage Differential 30- up to 100 Mbps
  • Power Dissipation at 100 Mbps
    • Driver: 50 mW Typical
    • Receiver: 30 mW Typical
  • Meets or Exceeds Current Revision of M-LVDS Standard TIA/EIA–899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1-V to 3.4-V Common-Mode Voltage Range Allows Data Transfer With up to 2 V of Ground Noise
  • Type-1 Receivers Incorporate 25 mV of Hysteresis
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Operates From a Single 3.3-V Supply
  • Propagation Delay Times Typically 2.3 ns for Drivers and 5 ns for Receivers
  • Power-Up/Down Glitch-Free Driver
  • Driver Handles Operation Into a Continuous Short Circuit Without Damage
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
  • 200-Mbps Devices Available (SN65MLVD201, 203, 206, and 207)

The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second) units.

This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. Driver output current has been increased to support doubly-terminated, 50- load multipoint applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.

Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of –1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output oscillations in the presence of noise. Type-2 receivers include an offset threshold to detect open-circuit, idle-bus, and other fault conditions, and provide a known output state under these conditions.

The intended application of these devices is in half-duplex or multipoint baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics).

These devices are characterized for operation from –40°C to 85°C.

This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. Driver output current has been increased to support doubly-terminated, 50- load multipoint applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.

Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of –1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output oscillations in the presence of noise. Type-2 receivers include an offset threshold to detect open-circuit, idle-bus, and other fault conditions, and provide a known output state under these conditions.

The intended application of these devices is in half-duplex or multipoint baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics).

These devices are characterized for operation from –40°C to 85°C.

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技術文件

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類型 標題 日期
* Data sheet SN65MLVD200/2/4/5: Multipoint-LVDS Line Drivers and Receivers datasheet (Rev. E) 2003年 4月 25日
Application note Introduction to M-LVDS (TIA/EIA-899) (Rev. A) 2013年 1月 3日
User guide Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. B) 2004年 4月 5日
Application note M-LVDS Signaling Rate Versus Distance 2003年 4月 9日
Application note Interoperability of M-LVDS and BusLVDS 2003年 2月 6日
User guide 200 Mbps Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. A) 2002年 12月 20日
Application note Wired-Logic Signaling with M-LVDS 2002年 10月 31日
User guide Multipoint-Low Voltage Differential Signaling (M-LVDS) Evaluation Module 2002年 3月 4日
Application note TIA/EIA-485 and M-LVDS, Power and Speed Comparison 2002年 2月 20日

設計與開發

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模擬型號

SN65MLVD202 IBIS Model (Rev. A)

SLLC087A.ZIP (5 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 14 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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