封裝資訊
| 封裝 | 引腳 SOIC (D) | 14 |
| 作業溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送包裝 2,500 | LARGE T&R |
SN65MLVD202A 的特色
- Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates (1) up to 100Mbps, Clock Frequencies up to 50MHz
- Type-1 Receivers Incorporate 25mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)
- Type-2 Receivers Provide an Offset (100mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- –1V to 3.4V of Common-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise
- Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
- 200Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)
- Bus Pin ESD Protection Exceeds 8kV
- Packages Available:
- 8-Pin SOIC SN65MLVD200A, SN65MLVD204A
- 14-Pin SOIC SN65MLVD202A, SN65MLVD205A
- Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices
(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
SN65MLVD202A 的說明
The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.
The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.
The devices are characterized for operation from –40°C to 85°C.