56-pin (DL) package image

SN74ALVCH16270DL 現行

具有 3 態輸出的 12 位元至 24 位元暫存匯流排交換器

定價

數量 價格
+

額外包裝數量 | 包裝類型選項 這些產品完全相同,但包裝類型不同

SN74ALVCH16270DLR 現行 custom-reels 客製 可提供客製捲盤
包裝數量 | 運送包裝 1,000 | LARGE T&R
庫存
數量 | 價格 1ku | +

品質資訊

等級 Catalog
RoHS
REACH
引腳鍍層 / 焊球材質 NIPDAU
MSL 等級 / 迴焊峰值 Level-1-260C-UNLIM
品質、可靠性
及包裝資訊

內含資訊:

  • RoHS
  • REACH
  • 產品標記
  • 引腳鍍層 / 焊球材質
  • MSL 等級 / 迴焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中可靠性監測
檢視或下載
其他製造資訊

內含資訊:

  • 晶圓廠位置
  • 組裝地點
檢視

出口分類

*僅供參考

  • 美國 ECCN:EAR99

更多SN74ALVCH16270資訊

封裝資訊

封裝 | 引腳 SSOP (DL) | 56
作業溫度範圍 (°C) -40 to 85
包裝數量 | 運送包裝 20 | TUBE

SN74ALVCH16270 的特色

  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

SN74ALVCH16270 的說明

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN\ inputs are low. The select (SEL)\ line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA\ inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). The control terminals are registered to synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from –40°C to 85°C.

定價

數量 價格
+

額外包裝數量 | 包裝類型選項 這些產品完全相同,但包裝類型不同

SN74ALVCH16270DLR 現行 custom-reels 客製 可提供客製捲盤
包裝數量 | 運送包裝 1,000 | LARGE T&R
庫存
數量 | 價格 1ku | +

包裝類型選項

您可依零件數量選擇不同包裝類型選項,包含完整捲盤、客製化捲盤、剪切捲帶、承載管或盤。

客製化捲盤是從一個捲盤上剪切下來的連續剪切捲帶,以維持批次和日期代碼可追溯性,依要求剪切至確切數量。依照業界標準,銅墊片會在剪切捲帶兩側連接 18 英吋前後導帶,以直接送至自動組裝機器。針對客製化捲盤訂單,TI 將酌收捲帶封裝費用。

剪切捲帶是從捲盤剪切下來的一段捲帶。TI 可能使用多條剪切捲帶或承載盒,以滿足訂單要求數量。

TI 常以盒裝或管裝、盤裝方式運送承載管裝置,視現有庫存而定。所有捲帶、管或樣本盒之封裝,皆符合公司內部靜電放電與防潮保護包裝要求。

進一步了解

可提供批次和日期代碼選擇

在購物車中加入數量,並開始結帳流程以檢視可用選項,從現有庫存中選擇批次或日期代碼。

進一步了解