產品詳細資料

Technology family GTL Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTL Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 64 137.7 mm² 17 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Translates Between GTL/GTL+ Signal Level and LVTTL Logic Levels
  • High-Drive (100 mA), Low-Output-Impedance (12 ) Bus Transceiver (B Port)
  • Edge-Rate-Control Input Configures the B-Port Output Rise and Fall Times
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

OEC, UBT, and Widebus are trademarks of Texas Instruments.

  • Member of the Texas Instruments Widebus™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Translates Between GTL/GTL+ Signal Level and LVTTL Logic Levels
  • High-Drive (100 mA), Low-Output-Impedance (12 ) Bus Transceiver (B Port)
  • Edge-Rate-Control Input Configures the B-Port Output Rise and Fall Times
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

OEC, UBT, and Widebus are trademarks of Texas Instruments.

The SN74GTL1655 is a high-drive (100 mA), low-output-impedance (12 ) 16-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 8-bit transceivers and combines D-type flip-flops and D-type latches to allow for transparent, latched, and clocked modes of data transfer similar to the ’16501 function. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching.

The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels but are not 5-V tolerant. VREF is the reference input voltage for the B port.

This device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals, but with a common clock and output enable inputs for both transceiver words.

Data flow for each word is determined by the respective latch enables (LEAB and LEBA), output enables (OEAB\ and OEBA\), and clock (CLK). The output enables (1OEAB\, 1OEBA\, 2OEAB\, and 2OEBA\) control byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK low-to-high transition. When OEAB\ is low, the outputs are active. With OEAB\ high, the outputs are in the high-impedance state.

Data flow for the B-to-A direction is identical, but uses OEBA\, LEBA, and CLK. Note that CLK is common to both directions and both 8-bit words. (OE)\ is also common and is used to disable all I/O ports simultaneously.

The SN74GTL1655 has adjustable edge-rate control (VERC ). Changing VERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74GTL1655 is a high-drive (100 mA), low-output-impedance (12 ) 16-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 8-bit transceivers and combines D-type flip-flops and D-type latches to allow for transparent, latched, and clocked modes of data transfer similar to the ’16501 function. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching.

The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels but are not 5-V tolerant. VREF is the reference input voltage for the B port.

This device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals, but with a common clock and output enable inputs for both transceiver words.

Data flow for each word is determined by the respective latch enables (LEAB and LEBA), output enables (OEAB\ and OEBA\), and clock (CLK). The output enables (1OEAB\, 1OEBA\, 2OEAB\, and 2OEBA\) control byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK low-to-high transition. When OEAB\ is low, the outputs are active. With OEAB\ high, the outputs are in the high-impedance state.

Data flow for the B-to-A direction is identical, but uses OEBA\, LEBA, and CLK. Note that CLK is common to both directions and both 8-bit words. (OE)\ is also common and is used to disable all I/O ports simultaneously.

The SN74GTL1655 has adjustable edge-rate control (VERC ). Changing VERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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類型 標題 日期
* Data sheet 16-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceiver With Live Insertion datasheet (Rev. I) 2001年 12月 19日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
User guide GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) 2001年 9月 15日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) 1997年 3月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

HSPICE MODEL OF SN74GTL1655

SCEJ211.ZIP (119 KB) - HSpice Model
模擬型號

SN74GTL1655 IBIS Model (Rev. C)

SCEM061C.ZIP (33 KB) - IBIS Model
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TSSOP (DGG) 64 Ultra Librarian

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