SN74LV123A

Name: SN74LV123A
Brand: TI
SKU: SN74LV123A
Price: 0.182 USD

現行

雙路可重觸發單穩多頻振盪器

立即訂購

產品規格表

document-pdfAcrobat SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs datasheet (Rev. Q) (英文) PDF | HTML

SN74LV123A

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

2

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Technology family

LV-A

Input type

Schmitt-Trigger

Output type

Push-Pull

Supply current (µA)

20

IOL (max) (mA)

12

IOH (max) (mA)

-12

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

2

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Technology family

LV-A

Input type

Schmitt-Trigger

Output type

Push-Pull

Supply current (µA)

20

IOL (max) (mA)

12

IOH (max) (mA)

-12

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

VQFN (RGY)

16

14 mm² 4 x 3.5

2-V to 5.5-V V_CC Operation
Maximum t_pd of 11 ns at 5 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I_off Supports Partial-Power-Down Mode Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

2-V to 5.5-V V_CC Operation
Maximum t_pd of 11 ns at 5 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I_off Supports Partial-Power-Down Mode Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V_CC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V_CC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

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	類型	標題		日期
*	Data sheet	SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs datasheet (Rev. Q)	PDF \| HTML	2015年 8月 31日
	Product overview	Configurable Timed Reset Using Discrete Logic (Rev. A)	PDF \| HTML	2023年 5月 2日
	Application note	Detect and Reset an Unresponsive Controller	PDF \| HTML	2023年 3月 21日
	Application note	Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A)	PDF \| HTML	2020年 3月 13日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日

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使用指南: PDF | HTML

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14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

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模擬型號

HSPICE Model for SN74LV123A

SCLJ019.ZIP (111 KB) - HSpice Model

下載

模擬型號

SN74LV123A IBIS Model (Rev. A)

SCEM125A.ZIP (21 KB) - IBIS Model

下載

模擬型號

SN74LV123A PSpice Model (Rev. C)

SCEM569C.ZIP (384 KB) - PSpice Model

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封裝	針腳	CAD 符號、佔位空間與 3D 模型
SOIC (D)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian
SSOP (DB)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
TVSOP (DGV)	16	Ultra Librarian
VQFN (RGY)	16	Ultra Librarian

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SN74LV123A

雙路可重觸發單穩多頻振盪器

SN74LV123A

產品詳細資料

技術文件

設計與開發

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

HSPICE Model for SN74LV123A

SN74LV123A IBIS Model (Rev. A)

SN74LV123A PSpice Model (Rev. C)

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