48-pin (PFB) package image

SRC4392IPFB 現行

高端整合式取樣速率轉換器

定價

數量 價格
+

額外包裝數量 | 包裝類型選項 這些產品完全相同,但包裝類型不同

SRC4392IPFBR 現行 custom-reels 客製 可提供客製捲盤
包裝數量 | 運送包裝 1,000 | LARGE T&R
庫存
數量 | 價格 1ku | +

品質資訊

等級 Catalog
RoHS
REACH
引腳鍍層 / 焊球材質 NIPDAU
MSL 等級 / 迴焊峰值 Level-2-260C-1 YEAR
品質、可靠性
及包裝資訊

內含資訊:

  • RoHS
  • REACH
  • 產品標記
  • 引腳鍍層 / 焊球材質
  • MSL 等級 / 迴焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中可靠性監測
檢視或下載
其他製造資訊

內含資訊:

  • 晶圓廠位置
  • 組裝地點
檢視

出口分類

*僅供參考

  • 美國 ECCN:EAR99

封裝資訊

封裝 | 引腳 TQFP (PFB) | 48
作業溫度範圍 (°C) -40 to 85
包裝數量 | 運送包裝 250 | JEDEC TRAY (5+1)

SRC4392 的特色

  • Two-Channel Asynchronous Sample Rate Converter (SRC)
    • Dynamic Range with –60dB Input (A-Weighted): 144dB typical
    • Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: –140dB typical
    • Supports Audio Input and Output Data Word Lengths Up to 24 Bits
    • Supports Input and Output Sampling Frequencies Up to 216kHz
    • Automatic Detection of the Input-to-Output Sampling Ratio
    • Wide Input-to-Output Conversion Range:
      16:1 to 1:16 Continuous
    • Excellent Jitter Attenuation Characteristics
    • Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates
    • Digital Output Attenuation and Mute Functions
    • Output Word Length Reduction
    • Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags
  • Digital Audio Interface Transmitter (DIT)
    • Supports Sampling Rates Up to 216kHz
    • Includes Differential Line Driver and
      CMOS Buffered Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Status Registers and Interrupt Generation for Flag and Error Conditions
  • User-Selectable Serial Host Interface: SPI or Philips I2C™
    • Provides Access to On-Chip Registers and Data Buffers

    U.S. Patent No. 7,262,716

  • Digital Audio Interface Receiver (DIR)
    • PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz
    • Includes Four Differential Input Line Receivers and an Input Multiplexer
    • Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
    • Audio CD Q-Channel Sub-Code Decoding and Data Buffer
    • Status Registers and Interrupt Generation for Flag and Error Conditions
    • Low Jitter Recovered Clock Output
  • Two Audio Serial Ports (Ports A and B)
    • Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
    • Slave or Master Mode Operation with Sampling Rates up to 216kHz
    • Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
    • Supports Audio Data Word Lengths Up to
      24 Bits
  • Four General-Purpose Digital Outputs
    • Multifunction Programmable Via Control Registers
  • Extensive Power-Down Support
    • Functional Blocks May Be Disabled Individually When Not In Use
  • Operates From +1.8V Core and +3.3V I/O Power Supplies
  • Packages:
    • QFN-40
    • Small TQFP-48 Package, Compatible with the SRC4382 and DIX4192

SRC4392 的說明

The SRC4392 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The SRC4392 combines a high-performance, two-channel, asynchronous sample rate converter (SRC) with a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.

The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports, DIT, and SRC may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz.

The SRC4392 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.

The SRC4392 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The SRC4392 is available in a QFN-40 and a lead-free, TQFP-48 package. The TQFN-48 is pin- and register-compatible with the Texas Instruments SRC4382 and DIX4192 products.

定價

數量 價格
+

額外包裝數量 | 包裝類型選項 這些產品完全相同,但包裝類型不同

SRC4392IPFBR 現行 custom-reels 客製 可提供客製捲盤
包裝數量 | 運送包裝 1,000 | LARGE T&R
庫存
數量 | 價格 1ku | +

包裝類型選項

您可依零件數量選擇不同包裝類型選項,包含完整捲盤、客製化捲盤、剪切捲帶、承載管或盤。

客製化捲盤是從一個捲盤上剪切下來的連續剪切捲帶,以維持批次和日期代碼可追溯性,依要求剪切至確切數量。依照業界標準,銅墊片會在剪切捲帶兩側連接 18 英吋前後導帶,以直接送至自動組裝機器。針對客製化捲盤訂單,TI 將酌收捲帶封裝費用。

剪切捲帶是從捲盤剪切下來的一段捲帶。TI 可能使用多條剪切捲帶或承載盒,以滿足訂單要求數量。

TI 常以盒裝或管裝、盤裝方式運送承載管裝置,視現有庫存而定。所有捲帶、管或樣本盒之封裝,皆符合公司內部靜電放電與防潮保護包裝要求。

進一步了解

可提供批次和日期代碼選擇

在購物車中加入數量,並開始結帳流程以檢視可用選項,從現有庫存中選擇批次或日期代碼。

進一步了解