封裝資訊
| 封裝 | 引腳 VSON (DRB) | 8 |
| 作業溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送包裝 3,000 | LARGE T&R |
TLIN2021A-Q1 的特色
- AEC-Q100 (Grade 1) Qualified for automotive applications
- Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO 17987–4 electrical physical layer (EPL) specification
- Compliant to SAE J2602-1 LIN Network for Vehicle Applications
- Functional Safety-Capable
- Support for 12-V and 24-V applications
- Wide input operational voltage range:
- VSUP range from 4.5 V to 45 V
- LIN transmit data rate up to 20 kbps
- LIN receive data rate up to 100 kbps
- Operating modes: Normal, Standby and Sleep
- Low-power mode wake-up support with source recognition:
- Remote wake-up over the LIN bus
- Local wake-up via the WAKE pin
- Local wake-up via EN
- Integrated 45-kΩ LIN pull-up resistor
- Control of system-level power using the INH pin
- Power-up/down glitch-free operation on LIN bus and RXD output
- Protection features: ±60 V LIN bus fault tolerant, 58 V load dump support, undervoltage protection on VSUP, TXD dominant state time-out, thermal shutdown, unpowered node or ground disconnection fail-safe at system level
- Junction temperature from -40°C to 150°C
- Available in 8-pin SOIC, VSON with wettable flanks, and SOT23 packages
TLIN2021A-Q1 的說明
The TLIN2021A-Q1 is a local interconnect network (LIN) physical layer transceiver. LIN is a low-speed universal asynchronous receiver transmitter (UART) communication protocol that supports automotive in-vehicle networking.
The TLIN2021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME).
The TLIN2021A-Q1 is designed to support 12-V and 24-V applications with a wide input voltage operating range. The device supports low-power sleep mode, as well as wake-up from low-power mode through wake over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the device INH output pin.