TXG1021-Q1
- AEC-Q100 qualified for automotive applications
- Supports DC shifts up to ±10V
- AC Noise Rejection of 20VPP up to 45MHz
- CMTI of 1kV/µs
- Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
- Greater than 250Mbps
- Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
- Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
- 4, 2, 1 channel devices with multiple configurations will be available
- Two device variants:
- TXG1020-Q1: 2 forward
- TXG1021-Q1: 1 forward, 1 reverse
- Supports VCC disconnect feature (I/Os are forced into high-Z)
- Schmitt-trigger inputs allows for slow and noisy signals
- Inputs with integrated static pull-down resistors prevent channels from floating
- Operating temperature from –40°C to +125°C
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 4000V human-body model
- 500V charged-device model
- Package options provided:
- DSG (WSON-8)
- DDF (SOT-8)
- D (SOIC-8)
The TXG102x-Q1 is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±10V. Compared to traditional level shifters, the TXG102x-Q1 family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.
VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <40nA when VCC to GND is shorted.
The TXG102x-Q1 device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 20VPP up to 45MHz (Figure 7-3). This device can support multiple interfaces such as UART, GPIO, and JTAG.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TXG102x-Q1 2-bit , ± 10V Ground-Level Translator datasheet | PDF | HTML | 2025年 5月 30日 |
Technical article | 接地電位不均?以新型的接地電平轉換器解決偏移挑戰 (Rev. A) | PDF | HTML | 2025年 6月 5日 | |
Application brief | Not All Grounds Are 0V | PDF | HTML | 2025年 5月 21日 | |
Product overview | TI's Latest Ground-Level Translators | PDF | HTML | 2025年 5月 7日 |
設計與開發
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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
訂購與品質
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