RF PLLs & synthesizers – Technical documents
RF phase locked loop (PLL) and synthesizers selection guides, application notes, white papers, and much more.
Featured application notes
LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs
Using a programmable input multiplier allows the spurs of a PLL to be drastically improved, especially for the worst case VCO frequencies. This feature is included on some of our PLLs, such as the LMX2571, LMX2582 and LMX2592.
Clocking Optimization for RF Sampling Analog-to-Digital Converters (Rev. A)
When designing a system with an ADC, make sure that the jitter of the clock does not degrade the signal-to-noise ratio of the ADC. High-performance synthesizers used with RF sampling ADCs get the best system performance.
Application note
Showing 3 of 28 results View All 28 Results
| Title | Type | Size (KB) | Date |
|---|---|---|---|
| Clocking Optimization for RF Sampling Analog-to-Digital Converters (Rev. A) | 668 | 07 Apr 2021 | |
| Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization | 2763 | 11 Nov 2020 | |
| Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter | 2758 | 30 Sep 2020 |
Selection guide
Showing 2 of 2 results
| Title | Type | Size (KB) | Date |
|---|---|---|---|
| TI Space Products (Rev. H) | 1412 | 27 Jan 2021 | |
| TI Components for Aerospace and Defense Guide (Rev. E) | 9699 | 22 Mar 2017 |