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8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)


Package | PIN: FCBGA (AAV) | 144
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $1,105.10
10-24 $1,041.96
25-99 $1,018.27
100+ $897.00


  • ADC Core:
    • 8-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to3.2 GSPS inDual-Channel Mode
  • Performance Specifications (fIN = 997 MHz):
    • ENOB: 7.8 Bits
    • SFDR:
      • Dual-Channel Mode: 67 dBFS
      • Single-Channel Mode: 62 dBFS
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable InputFrequency Range: >10 GHz
    • Full-Scale Input Voltage(VFS, Default): 0.8 VPP
    • AnalogInput Common-Mode (VICM): 0 V
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • SimplifiesSynchronization and Interleaving
    • Temperature and Voltage InvariantDelays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for SampleMarking
  • JESD204B Serial Data Interface:
    • Supports Subclass 0 and 1
    • Maximum Lane Rate: 12.8 Gbps
    • Up to 16 Lanes Allows ReducedLane Rate
  • Power Consumption: 2.8 W
  • Power Supplies: 1.1 V, 1.9 V

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Texas Instruments  ADC08DJ3200AAV

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digitalconverter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channelmode, the ADC08DJ3200 can sample up to 3200 MSPS and upto 6400MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) andNyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needsof both high channel count or wide instantaneous signal bandwidth applications. Full-power inputbandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- andsingle-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequencyagile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16serialized lanes and subclass-1 compliance for deterministic latency and multi-devicesynchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-offbit rate and number of lanes. At 5 GSPS, only four total lanes are requiredrunning at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps.Innovative synchronization features, including noiseless aperture delay(TAD) adjustment and SYSREF windowing, simplify system design for phasedarray radar and MIMO communications.