Packaging information
| Package | Pins WQFN (RTA) | 40 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the ADC31JB68
- Single Channel
- 16-Bit Resolution
- Maximum Clock Rate: 500 Msps
- Small 40-Pin QFN Package (6 x 6 mm)
- Input Buffer Input Bandwidth (3 dB): 1300 MHz
- Aperture Jitter: 80 fs
- On Chip Clock Divider: /1, /2, /4
- On Chip Dither
- Consistent Dynamic Performance Using Foreground and Background Calibration
- Input Amplitude and Phase Adjustment
- Input Full Scale: 1.7 Vpp
- Power Supplies: 1.2/1.8/3 V
- JESD204B Interface
- Subclass 1 Compliant
- 2 Lanes at 5 Gbps
- Support for Multi-chip Synchronization
- Key
Specifications
- Power Dissipation: 915 mW at 500 Msps
-
Performance at fin = 210 MHz at –1 dBFS
- SNR: 69.3 dBFS
- NSD: –153.3 dBFS/Hz
- SFDR: 80 dBc
- Non-HD2,HD3: –91 dBFS
- Performance at fin = 450 MHz at –1
dBFS
- SNR: 67 dBFS
- NSD: –151 dBFS/Hz
- SFDR: 77 dBc HD2,3
- Non-HD2,HD3: –89 dBFS
Description for the ADC31JB68
The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.
The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.
This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.
The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.