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ADC3244IRGZR ACTIVE

Dual-channel 14-bit 125-MSPS analog-to-digital converter (ADC)

US ECCN: 3A991C3 US/Local Export Classification Number

Inventory:

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-3-260C-168 HR
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
VQFN (RGZ) | 48 2,500 | LARGE T&R -40 to 85
Package | Pins VQFN (RGZ) | 48
Package qty | Carrier: 2,500 | LARGE T&R
Operating temperature range (°C) -40 to 85
View TI packaging information

Features for the ADC3244

  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface (SLVDS)
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

Description for the ADC3244

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

Pricing


Qty Price (USD)
1-99 40.574
100-249 36.066
250-999 29.648
1,000+ 26.519

Additional package qty | carrier options

Package qty | Carrier 250 | SMALL T&R
Inventory
Qty | Price (USD) 1ku | 27.905 1-99 42.695 100-249 37.951 250-999 31.198 1,000+ 27.905