Features for the ADC32J44EVM
- Single 1.8V supply to simplify power requirements
- Flexible input clock buffer with 1/2/4 divider to simplify clocking
- On chip dither to improve SFDR
- JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
- Supports subclasses 0, 1, 2 for synchronization and compatibility
- Pin compatibility with 12/14b and dual/quad devices
Description for the ADC32J44EVM
The ADC32J44 EVM demonstrates the performance of a low power dual 125Msps 14 bit ADC. It includes the ADC32J44 device, an optional DC-coupled THS4541 active interface signal path, JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm single ended signal source. If a DC coupled path is desired an optional path is provided using the THS4541. This can be selected by moving some solder jumpers. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI.