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AFE7422IABJ

Dual-channel RF-sampling AFE with 14-bit 9-GSPS DAC and 3-GSPS ADC with bypass mode

Availability: 626

Packaging

Package | PIN: FCBGA (ABJ) | 400
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $1,287.40
10-24 $1,264.90
25-99 $1,253.65
100+ $1,249.90

Features

  • Two, 14-bit, 9-GSPS DACs
    • Up to1200-MHz signal bandwidth
    • 1 DSA per channel tunes outputpower
  • Two, 14-Bit, 3-GSPS ADCs
    • Up to 1500-MHzsignal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance atfIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamicrange
    • RF and digital powerdetectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • Bypassable quad DDC per ADC
    • 3-phase coherent 32-bit NCOs perDDC
    • Decimation ratio: 2x to32x
  • Transmit digital signal path:
    • QuadDUC per DAC with 32-bit NCOs
    • Interpolation ratio: 6x to 36x
    • Sin(x)/xcorrection and configurable delay
    • Power amplifier protection(PAP)
  • JESD204B interface:
    • 8transceivers at up to 15 Gbps
    • Subclass 1 multichipsynchronization
  • Clocks:
    • InternalPLL and VCO with bypass option
    • Clock output up to 3 GHz with clockdivider
  • DAC power dissipation: 1.8 W/ch at 9 GSPS
  • ADC power dissipation: 1.9 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch

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Texas Instruments  AFE7422IABJ

The AFE7422 is a dual-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit,9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enablesdirect RF sampling into the C-band frequency range without the need for additional frequencyconversions stages. This improvement in density and flexibility enables high-channel-count,multimission systems.

The DAC signal paths support interpolation and digital up conversion options that deliverup to 1200 MHz of signal bandwidth. Thedifferential output path includes a digital step attenuator (DSA), which enables tuning of outputpower.

Each ADC input path includes a dual DSA and RF and Digital power detectors.Flexible decimation options provide optimization of data bandwidth and adecimation bypass mode is also available for widest signal bandwidth.

An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.