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CD54HC107F3A ACTIVE

High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset

Same as: 5962-8515401CA   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Inventory: 229
Lot and date code selection may be available
 

Quality information

RoHS No
REACH Affected
Lead finish / Ball material SNPB
MSL rating / Peak reflow N/A for Pkg Type
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
View or download

Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
CDIP (J) | 14 1 | TUBE
-55 to 125
Package | Pins CDIP (J) | 14
Package qty | Carrier: 1 | TUBE
Operating temperature range (°C) -55 to 125
View TI packaging information

Features for the CD54HC107

  • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
  • Asynchronous Reset
  • Complementary Outputs
  • Buffered Inputs
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Description for the CD54HC107

The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.

The HCT logic family is functionally as well as pin compatible with the standard LS family.

Pricing


Qty Price (USD)
1-99 13.76
100-249 12.019
250-999 9.267
1,000+ 8.289

Additional package qty | carrier options

Package qty | Carrier 1 | TUBE
Inventory 229
Qty | Price (USD) 1ku | 8.289 1-99 13.76 100-249 12.019 250-999 9.267 1,000+ 8.289