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CD54HC194F3A ACTIVE

High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

Same as: 5962-8682601EA   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Inventory: 663
Lot and date code selection may be available
 

Quality information

RoHS No
REACH Affected
Lead finish / Ball material SNPB
MSL rating / Peak reflow N/A for Pkg Type
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
View or download

Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
CDIP (J) | 16 1 | TUBE
-55 to 125
Package | Pins CDIP (J) | 16
Package qty | Carrier: 1 | TUBE
Operating temperature range (°C) -55 to 125
View TI packaging information

Features for the CD54HC194

  • Four Operating Modes
    • Shift Right, Shift Left, Hold and Reset
  • Synchronous Parallel or Serial Operation
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Asynchronous Master Reset
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Description for the CD54HC194

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.

Pricing


Qty Price (USD)
1-99 23.072
100-249 20.154
250-999 15.539
1,000+ 13.899

Additional package qty | carrier options

Package qty | Carrier 1 | TUBE
Inventory 663
Qty | Price (USD) 1ku | 13.899 1-99 23.072 100-249 20.154 250-999 15.539 1,000+ 13.899