CD54HC251F3A ACTIVE

Features for the CD54HC251

• Selects One of Eight Binary Data Inputs
• Three-State Output Capability
• True and Complement Outputs
• Typical (Data to Output) Propagation Delay of 14ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• Alternate Source is Philips
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Description for the CD54HC251

The ’HC251 and ’HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed silicon-gate CMOS technology. Together with the low power consumption of standard CMOS integrated circuits, they possess the ability to drive 10 LSTTL loads. The three-state feature makes them ideally suited for interfacing with bus lines in a bus-oriented system.

This multiplexer features both true (Y) and complement (Y\) outputs as well as an output enable (OE\) input. The OE\ must be at a low logic level to enable this device. When the OE\ input is high, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y\ outputs. The ’HCT251 logic family is speed, function, and pin-compatible with the standard ’LS251.