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CD74HC165M ACTIVE

High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

Same as: CD74HC165ME4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Inventory: 4,986
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View

Packaging information

Package | Pins Package qty | Carrier Operating temperature range (°C)
SOIC (D) | 16 40 | TUBE
-55 to 125
Package | Pins SOIC (D) | 16
Package qty | Carrier 40 | TUBE
Operating temperature range (°C) -55 to 125
View TI packaging information

Features for the CD74HC165

  • Buffered Inputs
  • Asynchronous Parallel Load
  • Complementary Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Description for the CD74HC165

The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q7 and Q\7) available from the last stage. When the parallel load (PL\) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL\ is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allow parallel-to-serial converter expansion by typing the Q7 output to the DS input of the succeeding device.

For predictable operation the LOW-to-HIGH transition of CE\ should only take place while CP is HIGH. Also, CP and CE\ should be LOW before the LOW-to-HIGH transition of PL to prevent shifting the data when PL\ goes HIGH.

Pricing


Qty Price (USD)
1-99 $0.571
100-249 $0.388
250-999 $0.299
1,000+ $0.199

Additional package qty | carrier options

Package qty | Carrier 2,500 | LARGE T&R
Inventory 136,828
Qty | Price (USD) 1ku | $0.090 1-99 $0.258 100-249 $0.176 250-999 $0.135 1,000+ $0.090
Custom reel may be available

Package qty | Carrier 250 | SMALL T&R
Inventory 550
Qty | Price (USD) 1ku | $0.314 1-99 $0.776 100-249 $0.597 250-999 $0.439 1,000+ $0.314