The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer thatsynchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator)frequency to one of the two reference clocks. The programmable pre-divider M and thefeedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock toVC(X)O
VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loopfilter components, the PLL loop bandwidth and damping factor can be adjust to meet different systemrequirements.
The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF),supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased systemredundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to fiveLVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that alloutputs are synchronized for low output skew.
All device settings, like outputs signaling, divider value, and input selection areprogrammable by SPI (3-wire serial peripheral interface). SPI allows individually control of thedevice settings.
The device operates in 3.3-V environment and is characterized for operation from –40°C to85°C.