text.skipToContent text.skipToNavigation


25- to 100-MHz, 10-bit & 12-bit FPD-Link III serializer

Availability: 750


Package | PIN: WQFN (RTV) | 32
Temp: S (-40 to 105)
Package qty | Carrier: 250 | SMALL T&R
Qty Price
1-99 $6.57
100-249 $5.74
250-999 $4.42
1,000+ $3.96


  • AEC-Q100 qualified for automotive applications
    • Device temperature grade 2: –40℃ to +105℃ ambient operatingtemperature
  • 25-MHz to 100-MHz input pixel clock support
  • Programmable data payload:
    • 10-Bit payload up to 100 MHz
    • 12-Bit payload up to 75 MHz
  • Continuous low latency bidirectional control interface channel with I2C support at 400 kHz
  • Embedded clock with DC-balanced coding to support AC-coupled interconnects
  • Capable of driving up to 15m coaxial or 20m shielded twisted-pair cables
  • Robust Power-Over-Coaxial (PoC) operation
  • 4 Dedicated general purpose input/output
  • 1.8-V, 2.8-V, or 3.3-V-compatible parallel inputs on serializer
  • Single power supply at 1.8 V
  • ISO 10605 and IEC 61000-4-2 ESD compliant
  • Small serializer footprint (5 mm × 5 mm)

All trademarks are the property of their respective owners.

Texas Instruments  DS90UB913ATRTVTQ1

The DS90UB913A-Q1 device offers an FPD-Link III interface with a high-speed forwardchannel and a bidirectional control channel for data transmission over a single coaxial cable ordifferential pair. The DS90UB913A-Q1 device incorporates differential signaling on both thehigh-speed forward channel and bidirectional control channel data paths. Theserializer/deserializer pair is targeted for connections between imagers and video processors in anECU (Electronic Control Unit). This device is ideally suited for driving video data requiring up to12-bit pixel depth plus two synchronization signals along with bidirectional control channelbus.

Using TI’s embedded clock technology allows transparent full-duplexcommunication over a single differential pair, carrying asymmetrical-bidirectional control channelinformation. This single serial stream simplifies transferring a wide data bus over PCB traces andcable by eliminating the skew problems between parallel data and clock paths. This significantlysaves system cost by narrowing data paths that in turn reduce PCB layers, cable width, andconnector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupledinterconnects.