|Package | PIN:||WQFN (RHS) | 48|
|Temp:||S (-40 to 105)|
- Qualified for automotive applications AEC-Q100
- Device temperature grade 2: –40℃ to +105℃ ambient operating temperaturerange
- Device HBM ESD classification level ±8kV
- Device CDMESD classification level C6
- 25-MHz to 100-MHz Input Pixel Clock Support
- Programmable data payload:
- 10-bit Payload up to 100-MHz
- 12-bit Payload up to 75-MHz
- Continuous low latency bidirectional control interface channel with I2C support at 400-kHz
- 2:1 Multiplexer to choose between two input images
- Capable of receiving over 15-m coaxial or 20-m shielded twisted-pair cables
- Robust Power-Over-Coaxial (PoC) operation
- Receive equalizer automatically adapts for changes in cable loss
- LOCK output reporting pin and @SPEED BIST diagnosis feature to validate link integrity
- Single power supply at 1.8-V
- ISO 10605 and IEC 61000-4-2 ESD compliant
- EMI/EMC mitigation with programmable spread spectrum (SSCG) and receiver staggered outputs
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Texas Instruments DS90UB914ATRHSTQ1
The DS90UB914A-Q1 device offers an FPD-Link III interface with a high-speed forwardchannel and a bidirectional control channel for data transmission over a single coaxial cable ordifferential pair. The DS90UB914A-Q1 device incorporates differential signaling on both thehigh-speed forward channel and bidirectional control channel data paths. The deserializer istargeted for connections between imagers and video processors in an ECU (Electronic Control Unit).This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus twosynchronization signals along with bidirectional control channel bus.
The deserializer features a multiplexer to allow selection between two input imagers, oneactive at a time. The primary video transport converts 10-bit or 12-bit data to a single high-speedserial stream, along with a separate low latency bidirectional control channel transport thataccepts control information from an I2C port and is independent of video blanking period.
Using TI’s embedded clock technology allows transparent full-duplexcommunication over a single differential pair, carrying asymmetrical-bidirectional control channelinformation. This single serial stream simplifies transferring a wide data bus over PCB traces andcable by eliminating the skew problems between parallel data and clock paths. This significantlysaves system cost by narrowing data paths that in turn reduce PCB layers, cable width, andconnector size and pins. In addition, the Deserializer inputs provide adaptive equalization tocompensate for loss from the media over longer distances. Internal DC-balanced encoding/decoding isused to support AC-coupled interconnects.