Packaging information
| Package | Pins WQFN (RUA) | 42 |
| Operating temperature range (°C) 0 to 70 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the HD3SS3412A
- Compatible With Multiple Interface Standards Operating up to 12 Gbps Including PCI Express Gen III and USB 3.0
- Wide –3-dB Differential BW of Over 8 GHz
- Excellent Dynamic Characteristics (at 4 GHz)
- Crosstalk = –35 dB
- Off Isolation = –19 dB
- Insertion Loss = –1.5 dB
- Return Loss = –11 dB
- Bidirectional "MUX/De-MUX" Type Differential Switch
- VDD Operating Range 3.3 V ±10%
- Small 3.5-mm × 9.0-mm, 42-Pin WQFN Package
- Common Industry Standard Pinout
- Supports XAUI and SGMII
Description for the HD3SS3412A
The HD3SS3412A device is a high-speed passive switch capable of switching four differential channels, including applications such as two full PCI Express x1 lanes from one source to one of two target locations in a PC or server application. With its bidirectional capability, the HD3SS3412A also supports applications that allow connections between one target and two source devices, such as a shared peripheral between two platforms. The HD3SS3412A has a single control line (SEL pin) which can be used to control the signal path between Port A and either Port B or Port C.
The HD3SS3412A is offered in an industry standard 42-pin WQFN package available in a common footprint shared by several other vendors. The device is specified to operate from a single supply voltage of 3.3 V over the full temperature range of 0°C to 70ºC.
The HD3SS3412A is a generic 4-CH high-speed MUX/de-MUX type of switch that can be used for routing high-speed signals between two different locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications, the HD3SS3412A will also support several other high-speed data protocols with a differential amplitude of <1800 mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.