|Package | Pins||VQFN (RGZ) | 48|
|Operating temperature range (℃)||I (-40 to 85)|
|Package qty | Carrier:||
250 | SMALL T&R
- One Digital Phase-Locked Loop (DPLL) With:
- Hitless Switching: ±50-ps PhaseTransient
- Programmable Loop Bandwidth WithFastlock
- Standards-Compliant Synchronization and HoldoverUsing a Low-Cost TCXO/OCXO
- Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
- 50-fs RMS Jitter at 312.5 MHz (APLL1)
- 125-fs RMS Jitter at 155.52 MHz (APLL2)
- Two Reference Clock Inputs
- Priority-Based InputSelection
- Digital Holdover on Loss ofReference
- Eight Clock Outputs With Programmable Drivers
- Up to Six Different OutputFrequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-VLVCMOS Output Formats
- EEPROM / ROM for Custom Clocks on Power-Up
- Flexible Configuration Options
- 1 Hz (1 PPS) to 800 MHz on Input andOutput
- XO/TCXO/OCXO Input: 10 to 100MHz
- DCO Mode: < 0.001 ppb/Step for Precise ClockSteering (IEEE 1588 PTP Slave)
- Advanced Clock Monitoringand Status
- I2C or SPIInterface
- PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
- 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
- Industrial Temperature Range: –40°C to +85°C
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The LMK05318 is a high-performancenetwork synchronizer clock device that provides jitter cleaning, clock generation, advanced clockmonitoring, and superior hitless switching performance to meet the stringent timing requirements ofcommunications infrastructure and industrial applications. The ultra-low jitter and high powersupply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed seriallinks.
The device can generate output clocks with 50-fs RMS jitter using TIs proprietary BulkAcoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and referenceinputs.
The DPLL supports programmable loop bandwidth for jitter and wander attenuation, whilethe two APLLs support fractional frequency translation for flexible clock generation. Thesynchronization options supported on the DPLL include hitless switching with phase cancellation,digital holdover, and DCO mode with less than 0.001-ppb (part per billion) frequency step size forprecision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1-PPS(pulse-per-second) reference input and support optional zero-delay mode on one output to achievedeterministic input-to-output phase alignment with programmable offset. The advanced referenceinput monitoring block ensures robust clock fault detection and helps to minimize output clockdisturbance when a loss of reference (LOR) occurs.
The device can use a commonly available low-frequency TCXO or OCXO to set the free-run orholdover output frequency stability per synchronization standards. Otherwise, the device can use astandard XO when free-run or holdover frequency stability and wander are not critical. The deviceis fully programmable through I2C or SPI interface and supports customfrequency configuration on power up with the internal EEPROM or ROM. The EEPROM is factorypre-programmed and can be programmed in-system if needed.