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Ultra-Low Jitter Programmable Oscillator with Internal EEPROM

Availability: 586


Package | PIN: QFM (SIA) | 6
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $21.98
10-24 $20.43
25-99 $19.72
100-249 $17.23
250-499 $16.39
500-749 $15.09
750-999 $13.54
1000+ $13.50


  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz onLMK61E07
    • PSRR: –70 dBc, Robust Supply Noise Immunity onLMK61E07
  • Flexible Output Format on LMK61E07
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm FromNominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range(–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
  • Default Frequency:
    • 70.656MHz

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Texas Instruments  LMK61E07-SIAT

The LMK61E07 family of ultra-low jitter PLLatinumTMprogrammable oscillators use fractional-N frequency synthesizers with integrated VCOs to generatecommonly used reference clocks. The output on LMK61E07 can be configured as LVPECL,LVDS, or HCSL. The device features self start-up from on-chip EEPROM to generate a factoryprogrammed default output frequency, or the device registers and EEPROM settings are fullyprogrammable in-system through I2C serial interface. The device providesfine and coarse frequency margining control through I2C serialinterface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes orglitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) forcompatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (Rdivider=1, doubler enabled) for compatibility with broadcast video requirements. The frequencymargining features also facilitate system design verification tests (DVT), such as standardscompliance and system timing margin testing.