Packaging information
| Package | Pins QFM (SIA) | 8 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the LMK61E0M
- Ultra-Low Noise, High
Performance
- Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M
- LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
- Total Frequency Tolerance of ±25 ppm
- System Level
Features
- Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
- Internal EEPROM: User Configurable Start-Up Settings
- Other Features
- Device Control: Fast Mode I2C up to 1000 kHz
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
- Default Frequency: 70.656 MHz
Description for the LMK61E0M
The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.