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156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

US ECCN: EAR99 US/Local Export Classification Number

Inventory: 7,347  

Quality information

RoHS Yes
Lead finish / Ball material NIAU
MSL rating / Peak reflow Level-3-260C-168 HR
Quality, reliability
& packaging information

Information included:

  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
QFM (SIA) | 8 250 | SMALL T&R
-40 to 85
Package | Pins QFM (SIA) | 8
Package qty | Carrier: 250 | SMALL T&R
Operating temperature range (°C) -40 to 85
View TI packaging information

Features for the LMK61E2

  • Ultra-Low Noise, High Performance
    • Jitter: 90 fs RMS Typical fOUT > 100 MHz
    • PSRR: –70 dBc, Robust Supply Noise Immunity
  • Flexible Output Format; User Selectable
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±50 ppm
  • System Level Features
    • Frequency Margining: Fine and Coarse
    • Internal EEPROM: User Configurable Default Settings
  • Other Features
    • Device Control: I2C
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
    • Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer

Description for the LMK61E2

The LMK61E2 device is an ultra-low jitter PLLatinum programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.

The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.

The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.


Qty Price (USD)
1-99 19.283
100-249 16.843
250-999 12.987
1,000+ 11.616